Well, now that we started with VHDL let’s see another example full of empirical rules that help us to take out the hindrance.
A VHDL project
The most important rules in these type of design are:
1) Don’t start to project without first reflected; take in consideration to project top-down. Think how we can divide our project and begin to specify the single module.
2) Where is possible we have to use selves-explanatory program structures as the case, because have the advantage of being formally elegant and to be self precisely, the disadvantage is that sometimes aren’t optimized, but the technology will help us more and more (more logical, more memory, more speed). Avoid the use of names of variable generics (read pippo or pluto or similar).
3) Use where is possible the control units – they are an extremely powerful tool that will help us.
4) The project must be strictly synchronous; I would add using a single clock (although probably this second imposition sometimes is difficult). Even the requirement to design a strictly synchronous hw can fail, but in this case you’ll have a difficulty design even for testing.
5) Every time you make an”important” modification don’t forget to make a check of whole project (you never know when you find another solution).
6) Remember to change the review before any radical change or implementation of the project. I usually copy the inter inter working directory rather than the individual files.
7) Make extensive usage of machine state, VHDL contains some constructs about machine state but in any case the structure is based on a switch (state diagram) and a status register.
I think is better to divide one machine state in more, in this way any MS is little and the interface is very clear.
Speaking about Machine State
From bibliography point of view the MS are divided in two:
- Moore MS
- Mealy MS
The difference between them is the generation of command (signals), in Mealy MS the signals depend by the state and by the input logic, in Moore MS the generated signals depend by state only. You can find a lot of references on the NET if you like.
MS Implementation
We would like here to implement two MS joined, the first one starts the second and wait for the completion of task.
The second one is waiting for the start condition and than, when it receives the start, execute a little state sequence and than send the ack to the calling MS.
In order to better clarify the purpose of MS we would like to implement two MS the first one acts as client and the second one is the server.
The client ask to the server to compute a certain time and the return with the ack, than the loop start again.
In the attached file you will find the example of the client project that include the vhdl file of the server. The server is developed in a different directory and here it is implemented as a project, than it was possible to compile and simulate the server in stand-alone.
Notes
If you study the examples you will find some implementation about the start and ack techniques.
The client send the start to the server, the start signal immediately respond with the busy status (start_flag), this will avoid that the client send another start.
This technique presents this problem:
- How long the start signal
The answer is than the server perform the derivative the rising edge of the signal and than set the busy flag.
In this way we can avoid to know the server status and the start signal can be long as we want.
A few hints at possible changes
The MS is implemented in two part, the fires is the switch and the second is the state register.
Sometimes the first part is referred as test logic.
The state register can be represented not only by a register but also as a counter, in this way you can have the following conditions:
- load (loading a new address)
- count (jump at +1)
- hold (stop on current address)
Imagine the branch instructions of a generic computer which:
if(sign =0 ) pc=pc+1 (sequence)
else pc=add; (jump)
Really, today we can develop a MS with more than one branch conditions, but we have to consider that the combinatorial logic consumes FPGA resources (plus decrease the toggle frequency).
For more informations click here: PROG.S.EL