Introduction
Welcome to this training module on Very Low-Jitter Encoded Clocking for High Speed ADCs Using the Analog Devices’ ADF4002 PLL. This training module discusses a design example using the ADF4002 frequency synthesizer to generate a very low-jitter clock to control sampling on Analog Devices’ AD9215 ADC.

Phase Locked Loop Basics

A phase-locked loop is a feedback system combining a voltage-controlled oscillator and a phase comparator so connected that the oscillator frequency (or phase) accurately tracks that of an applied frequency- or phase-modulated signal. Phase-locked loops can be used, for example, to generate stable output frequency signals from a fixed low-frequency signal. A simple block diagram of a PLL is shown in the figure. Typically a PLL consists of a phase detector (PD), a charge pump (CP), a loop filter, a voltage-controlled oscillator, and a feedback divider.

Phase Noise in PLL
The figure shows the main phase noise contributors in a PLL. For analysis, SREF is assumed as the noise that appears on the reference input to the phase detector. It is dependent on the reference divider circuitry and the spectral purity of the main reference signal. SN is the noise due to the feedback divider appearing at the frequency input to the phase detector. SCP is the noise due to the phase detector (depending on its implementation). And SVCO is the phase noise of the VCO. The overall phase noise at the output are added in an rms fashion to give the total noise of the system.

Optimizing PLL Design for Phase Noise

There are several ways to optimize PLL design for phase noise. Since phase noise is multiplied up from the PFD (reference frequency) at a rate of 20 logN, reducing N by a factor of 2 will improve system phase noise by 3 dB. Therefore the highest feasible PFD frequency should always be used. Choosing a higher frequency synthesizer is another way to improve the phase noise performance of PLL. Reducing the Rset increases the charge-pump current, which also reduces phase noise.

Why Low-Jitter Clocks for High Speed ADC
A low aperture jitter specification of an ADC is critical to achieving high levels of signal-to-noise ratios (SNR). Jitter generated by a clock source can cause the ADC's internal circuitry to falsely trigger the sampling time. This results in false sampling of the analog input amplitude, thus degrading the SNR of the ADC. Extremely low jitter sampling clocks must therefore be utilized so that the ADC performance is not degraded, because the total jitter is the root-sum-square of the internal converter aperture jitter and the external sampling clock jitter. However, the sampling clocks are more often specified in terms of phase noise rather than time jitter. In system designs requiring low jitter sampling clocks, the costs of low noise dedicated crystal oscillators is generally prohibitive. An alternative solution is to use a phase-locked-loop (PLL) in conjunction with a voltage-controlled oscillator to "clean up" a noisy system clock.

The ADF4002 Frequency Synthesizer
The ADF4002 frequency synthesizer consists of a low noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, and programmable N divider. The synthesizer works in a PLL, where a PFD compares a feed back frequency with a divided-down version of the reference frequency. The 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete PLL can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the part can be used as a standalone PFD and charge pump.

Phase Frequency Detector (PFD) of the AD4002
The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. The figure is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function, and minimizes phase noise and reference spurs. Two bits in the reference counter latch (ABP2 and ABP1) control the width of the pulse. The PFD’s output current pulses are filtered and integrated to generate a voltage. This voltage drives a voltage-controlled oscillator (VCO) to increase or decrease the output frequency so as to drive the PFD’s average output towards zero.

PLL Counters
The ADF4002 has a 13-bit N counter and a 14 bit R counter. The N counter allows a wide ranging division ratio in the PLL feedback counter. Division ratios from 1 to 8191 are allowed. The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed. The N counter makes it possible to generate output frequencies that are spaced only by the reference frequency divided by R.

Digital Lock Detect
Digital lock detect outputs either a CMOS logic high, indicating a locked PLL state, or a logic low, indicating an unlocked state. The simplified circuit diagram is shown in the figure. It works by measuring the phase error at the PFD inputs and using a window of 15 ns phase error to decide the lock status of the PLL. When the phase error at the PFD inputs on five or more consecutive cycles is inside the 15ns window, it considers the PLL to be in lock and outputs a logic high. When the phase error drifts outside of the loss of lock threshold (30 ns) on any subsequent PFD cycle, it registers an out-of-lock condition.

The AD4002 PLL Configurations

A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). This is particularly useful in either a clock cleaning application or a high performance local oscillator. In this application, both R and N counters are be programmed to 1. The very low normalized phase noise floor (−222 dBc/Hz) enables very low in-band phase noise levels. It is possible to operate the PFD up to a maximum frequency of 104 MHz. Since the R and N counters are equal to 1, the reference frequency equals the PFD; the charge pump output integrates into a stable control voltage for the VCXO, and the output from the VCXO is divided down to the desired PFD frequency using an external divider.

The AD4002 as High Speed ADC Clock
As discussed, high speed ADC, like the AD9215-80, is sensitive to the quality of the clock input. The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9215. The figure shows the ADF4002 with a VCXO to provide the encode clock for a high speed ADC. To realize a stable low jitter clock, use a 77.76 MHz, narrow band VCXO. This example assumes a 19.44 MHz reference clock. To minimize the phase noise contribution of the ADF4002, the smallest multiplication factor of 4 is used. Thus, the R divider is programmed to 1, and the N divider is programmed to 4. The charge pump output of the ADF4002 (Pin 2) drives the loop filter. The loop filter bandwidth is optimized for the best possible rms jitter. Too narrow a bandwidth allows the VCXO noise to dominate at small offsets from the carrier frequency. Too wide a bandwidth allows the ADF4002 noise to dominate at offsets where the VCXO noise is lower than the ADF4002 noise. Thus, the intersection of the VCXO noise and the ADF4002 in-band noise is chosen as the optimum loop filter bandwidth.

SPI Interface

In the verified circuit in previous page, the SPI® interface is used to control the ADF4002, and the USB interface helps control the operation of the AD9215-80. The controller board, HSC-ADC-EVALB-DCZ, sends back FFT information to the PC, if using an ADC analyzer, provides all conversion results from the ADC.

Additional Resources
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