Freescale’s multi-core communications platform represents a balanced approach to multi-core system-on-chip (SoC) design. It introduces an advanced on-chip connectivity fabric that is able to support up to 32 cores and beyond. The platform implements enhanced cores built on Power Architecture technology, each with private Level 2 (L2) cache, also known as backside cache. In addition, the platform extends our proven on-demand application acceleration capabilities with data path resource management functions. The multi-core platform is targeted to be implemented in 45 nm silicon on-insulator (SOI) process technology with a development path to 32 nm SOI technology.

While the multi-core platform is designed with aggressive performance targets, ease of use has also figured prominently in our platform definition. One of the significant obstacles in multi-core implementations today is programming efficiency and debugging. Freescale’s industry-leading ecosystem of tools and operating system vendors is mobilized to simplify multi-core development and debugging. Especially noteworthy is our collaboration with Virtutech to deliver a new hybrid simulation environment that allows programmers to migrate application software and evaluate performance in advance of prototype hardware.

Read more: A Smarter Approach to Multi-Core: Freescale’s Next-Generation Communications Platform