Programmable logic has now become a critical component for the design community, moving from the prototyping stage into general designs. These flexible ICs are now one of the first components to be specified at the beginning of the project because of a higher level of integrated features, such as embedded processors and high performance I/O options, and also because of the flexibility they offer, being able to cope easily with changing design requirements. They also offer a lower cost of entry over ASICs for projects, especially for low-medium volume, but increasingly for higher volume projects.

With the cost and power reduction benefits of the latest silicon manufacturing processes, programmable logic has progressed to the point it can replace the functionality of some, or even all of the digital logic devices on a PCB. A low-power FPGA will support one or more 32-bit RISC processors, offering up to 300DMIPS performance each, with peripherals and I/O interfaces in a system which can be designed to exact specifications. But how is a complex idea turned into a working design in a programmable device?

Altera’s Quartus II software offers a complete design flow for all the company’s FPGA and CPLD devices. This article will highlight some of those features and the benefits that they can offer the design engineer. The first step in the design process involves translating the design’s specification to something that the tools can understand; this can be done by HDL coding (AHDL, VHDL or Verilog), schematic design entry or by the design and integration of IP blocks using the integrated Megawizard IP configuration tools or the System On a Programmable Chip (SOPC) Builder graphical design entry tools. With SOPC builder, it is possible to create a custom processor design using the embedded Nios II processor in a very short time, and there is a growing range of SOPC Builder/Nios II processor compatible IP available to cut this design time down further.

Once the design entry has been completed, the design can then be compiled, downloaded and run on a board in a similar fashion to an off-the-shelf processor. Extra productivity is enabled through the reduction of compile times and facilitation of the integration of work by several developers on the same project by using incremental compilation.

For special requirements, the design entry features of Quartus II can be used to create components, which can then be integrated into the SOPC Builder’s component library using the Component Editor tool, which is part of SOPC Builder. In this way, custom logic can be quickly integrated with a processor-based system and then re-used in future designs.

Efficient design entry is however only half of the story; the design still requires testing and optimization. Quartus II includes a suite of power analysis tools that target the target device’s power saving architecture during the compilation process.

Design performance optimization is dealt with by the TimeQuest timing analysis feature that uses the ASIC industry standard Synopsys Design Constraints (SDC) format. Performance can be further boosted by the physical synthesis option that re-balances the design to map efficiently to the hardware and deliver optimal performance.

Quartus II can be licensed for free and includes all of the above features and a free version of Mentor’s ModelSim HDL simulator. The free version supports all Altera FPGA and CPLD devices apart from the larger high performance FPGA devices, for which a license fee is required. The software comes with comprehensive documentation and tutorials.

Source: Technology First online.