Here are some more I/O specific techniques for static consumption. Try reducing the switch capacitances and frequencies of I/Os, decouple I/Os when you're in the sleep mode. If this is impossible, power down the core and leave the VCCO applied. Try reducing the I/O voltage swing so keep the I/O drive as low as possible. Use lower voltage standards of your I/Os. Look at slew rate controls to reduce output switching current. Some FPGAs provide control over LVCMOS or LVTTL buffers. It can be configured for either a low noise or high speed performance. Also another possibility here is not to power I/O banks that are unused.

Also look for opportunities to lower your clock speed on your non-high performance clock domains. This reduced power consumption so that the dynamic power's directly proportional to the frequency of operation. Designers must determine if proportions are designed to be clocked at a lower rate. Also disable timing driven mapping and enable register retiming to optimization options you can find with the back end place and route tools will benefit power. The next set of reduction tips are more, again, design related and depend on how you write your HDL. Use signal encoding optimization of counters or state machines. Designers should be trying to target the embedded ASCI blocks of the device versus general fabric logic. So EBRs, DSPs, modern FPGAs will have a lower consumption over generic LUT or register logic.

In this arena, of course this is largely affecting the design itself. Your RTL or your source code actual contents of your design. One technique is to enable a synthesis area of optimization on all or a portion of your design. So by reducing the span of the device or the design across the device, a more closely placed design will help utilize fewer routing resources for less power consumption. The clock gating optimization and quadrant clocking is tied together. And then there are certainly approaches to use clock enable approaches, using gating clocks rather than operating on those on every cycle.

Here's an example of some of these products called Push Button optimization. So that the area of optimization technique and the register retiming approaches. In this case the impact of performance and power with a sample design implemented and an ECB2 device are measured. Using the area optimized synthesis, and register retiming, and the ICP lever design mapper, it can get power to drop around 20% and performance impact however on this case declined at about 10%.

Like simulation, FPGA thermal analysis is a verification flow that runs in parallel with the traditional FPGA implementation tools and then an ISP lever design flow for example. FPGA designers can estimate consumption at any stage, pre-synthesis, post-map, pre-route, post-route, and post-simulation. Use the ISP lever power calculator to estimate used resources, activity factors of logic blocks, and toggle rates of I/Os before synthesis and place a route, or designers can use it at a later stage as more implementation details are available.

Here's a screenshot of the power calculator UI. The calculator application inputs are at power parameters such as device characteristics, voltage, temperature, device variations, airflow, heat sink, resource utilization, activity and frequency. Uses all these factors to calculate the device consumption, and then it reports both the DC and AC portion of consumption. Once the device is imported or provided all the required information software produced power estimate and predict the junction temperature. Any time junction temperature is outside the limits specified in the data sheet, the viability of operating the device without some cooling technique must be reevaluated.

Here's an example equation from power calculator used to estimate consumption of the device look up tables. So in this expression, total AC Power for LUT is the power constant for the LUT blocks in millowatts per MHz that max frequency of the LUT clock measured in MHz, times the activity factory of the LUT, times the number of LUTs used in design. Activity factor is the percentage of switching activity. Power calculator use activity factors and toggle rates as a means to model dynamic power consumption.

AF percentages defined as the percentage of frequency or time that a signal is active or toggling the output. Most resources associated with a clock domain are running or toggling at some percentage of the frequency of which the clock is running. Activity factor can be calculated per each routing resource, output, or PFU. However, this can involve long calculations, so our general rule of thumb is that for design occupying roughly 30-70% of the device, an activity factor between 15-25% average value. The accurate value of activity factor depends on clock frequency, the stimulus to your design, and the final output. The key input term used for I/O consumption estimates is the I/O toggle rate. The activity of I/Os is determined by the signals provided by the user in the case of inputs, or is an output of the design in case of output signals. The rates at which I/Os toggle define their activity. The toggle rate or TR in MHz is the output as defined in the expression as shown.

Given an application where you must account for power consumption, power closure methodology should be adopted. The first step the designer should look for opportunities to create power-friendly RTL, high impact low effort practices include targeting embedded blocks, coding smaller state machines, organizing blocks in a manner that area optimization won't overly impact the performance. And if a device is a higher density 90 nanometer device, I/O programming and switching should be given extra scrutiny to save power. Next power friendly synthesis in place route optimizations like power registry time and area optimization should be applied. And finally, a robust test bench that reflects actual operating conditions will help build an accurate activity factor and toggle rate factors or post simulation analysis and that power estimation software.

The main point is this graph of the power rails. The power supply sequencing is an important consideration when you're managing the power budget of an FPGA. So for an example, there are three main power supplies that are required to power up the ECP2M device for proper operation. VCC, VCCAUX, and VCCIO8, BANK 8. Power management circuits have become an important companion on the circuit board to deal with power up and down sequencing. The sequencing circuit below illustrates how the Lattice impact POWR1014 device serves as a programmable controller with the various voltage rails attached to ECB2M FPGA. If there's a sample sequencing circuit, you can see the blue boxes here at DC to DC supplies and the input enables coming in from the controller. And they're sourcing up a variety of voltage rails with the FPGA on the right. There's supervisory and control signals coming in on the left and right, into the power manager.

The sequencing circuit as shown illustrates how the Lattice impact POWR1014 device serves as a programmable controller with the various voltage rails attached to ECB2M FPGA. If there's a sample sequencing circuit, you can see the blue boxes here at DC to DC supplies and the input enables coming in from the controller. And they're sourcing up a variety of voltage rails with the FPGA on the right. There's supervisory and control signals coming in on the left and right, into the power manager.

The ispPAC-POWR1014/A is a general-purpose power-supply monitor and sequence controller, incorporating both in-system programmable logic and in-system programmable analog functions implemented in non-volatile E2CMOS® technology. The ispPAC-POWR1014/A integrates many power management functions typically requiring multiple ICs.

In step one, the power manager is going to wait for an internal all-good signal to indicate its own power's available. In step two it turns on the 1.2, 2.5, and 3.3 supplies for the FPGA. In step three and four, once the VCC is crossed the VCC min value, it turns on the VCCAUX. Next it waits for all of these supplies to stabilize, and then a good power output signal is enabled to indicate that PGA is ready to be programmed. And in step seven, the sequence controller waits for the FPGA done to be issued from the ECB2M. At this -- if it exceeds using the internal timer, if it exceeds 520 milliseconds, the sub routine is run to initiate a shutdown. Finally step eight, the controller waits for any supply to fail or shutdown signal to go active. In step 9 through 14, this is the shut down sequence. The controller first disables the VCCAUX MOSFET and waits for it to reach 100 millivolts in the threshold. And then it powers off all of the other supplies and waits for a recycle signal to start the FPGA sequencing again.

One of the most critical factors in design is reducing the system power consumption, especially important for handheld devices and other modern electronic products. Low power design techniques depending on the device type targeted in the characteristics of the design to an understanding of the sources of the FPGA power consumption, static and dynamic, core and I/O will influence your power reduction strategy. Even the variety of voltage rails and sequencing requirements of modern FPGAs sequencing circuits and programmable controllers should be considered as part of any implementation.

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