Welcome to this module on the EPC2M family FPGA from Lattice. This module will provide an overview of the sources of FPGA power dissipation, design practices that can help reduce consumption and thus junction temperature, how to estimate and analyze power, and then some tips for managing a variety of power sources required for an FPGA implementation.

Introduction
Here are some key problems you might face with any FPGA power implementation. What will be the system level power supply requirements? What will be the current draw? What voltage levels will be required, and what power up/down issues will there be? What will be the thermal conditions of the device, and will it work reliably given the environment and the design I expect to run? Will I need to design in cooling mechanics for the board to counteract a hot part? And then, given the variety of voltage sources for core voltage, how can I manage sequencing? So while management of FPGA power has become an important consideration for many designers, increased dissipation can lead to larger power supplies and cooling systems. So, using good design techniques can help reduce the demand on power-hungry. Reducing power consumption increases the reliability of integrated circuits and can help lower the costs of production with leaner power supplies and fewer cooling requirements. Traditionally, FPGA designers have been concerned with timing and area efficiently; however, as FPGAs have moved more and more into the role of replacing ASSPs and ASICs, they have been pressured to developed lower-power designs, produce better power estimates earlier in the design flow, and then manage the sequence in a variety of core and I/O voltages that often accompany an FPGA implementation.

FPGA thermodynamics

Understanding FPGA thermodynamics will help you identify the high-impact, low-effort methods to reduce power. Total power is a function of certain types of sub-power producers, along with the characteristics of the process node and device packaging.

Powering electronic devices is often defined as the amount of work done by an electric current. Devices tend to convert work into heat, which is unfortunately not considered very useful for most applications unless your design is a heater or a light bulb. Power is expressed as Jules per second or Watts, given the equation -- equals V times I. CMOS FPGAs contribute to power dissipation from two primary sources, static and dynamic, and the total power dissipation is the sum of the static and dynamic power. The DC power depends on process, voltage, and temperature, or PVT variation. AC power is a strong function of the frequency and activity of the resources, and a weaker function of PVT. So Power Dynamic is expressed in the second equation: one-half beta times capacitance types VDD squared times frequency. The AC portion of the power consumption is associated with used resources of the device. The dynamic part of the power consumption. Dissipation is directly proportional to the frequency and activity at which the resource is running and the number of resource units used. From the equation, it becomes obvious that how power consumption can be influenced by lowering supply voltage -- the largest factor -- switch capacitance, switching activity of nodes, with a frequency of signal transitions.

This graph illustrates the relative consumption of static versus dynamic power consumption of the Lattice ECP15, a 130 nanometer FPGA, and the Lattice ECP2/M, a 90 nanometer. With a design that models 90% logic utilization, 100% utilization of embedded ASIC blocks like PLLs, memory, and DSP features, and around 80% utilization of I/Os using a mixture of LDCMOS1.2 and LDDS 2.3 DDR type signal standard. DC power can be further subdivided into the power consumption of the used and unused resources of FPGA.

In the older process nodes, CMOS FPGAs have a very low static DC power dissipation. Most energy was consumed during or by switching activity and by charge/discharge of load capacitances, largely a function of user design. But this convention changes around 90 nanometer process nodes and smaller. Transistor physics changes at smaller geometry such that the static leakage is now more significant. The graph here shows how static power is growing exponentially due to increasing transistor leakage. And the crossover point, where static power overtakes dynamic, is around 65 nanometer node. How does another semiconductor vendors address these issues largely in the respective fabrication processes and their transistor mix used in each device. This trend, however, makes adoption of a power verification methodology all the more important with 90 nanometer devices.

To illustrate the effects of node switching activity, this graph plots power consumption versus frequency with the sample hardware model described earlier in the ECP2/M and the ECP 130 nanometer device. The power benefit of the 90 nanometer FPGA is clear in this example.

This figure illustrates power consumption of the ECP2 versus the ECP, but looking at I/Os, here, based on the average output load capacitance and puffs. This plot demonstrates how power consumption of I/Os remains relatively constant between 130 and the 90 nanometer device families.

The relevant consumption by resource type also changes between process nodes. As an example, the figures illustrate contribution by resource, routing, logic -- such as gates and registers -- embedded block RAM, etc., in the 130 nanometer versus the 90 nanometer part. The charts demonstrate that while overall power consumption drops given the 90 nanometer device, the relative amount represented by I/Os increases. So at first glance, as FPGA technology process geometry shrinks, designers should benefit from reduced power consumption of smaller transistors and IC dies. However, this benefit could be many times offset by larger designs and higher speeds.

The primary sources of power: static, which is a function of PVT, dynamic, which is a function of activity -- and especially dynamic I/O activity should be accounted for when designing and verifying a design.

Heat is a key byproduct of work performed by a device and must be addressed to ensure an FPGA operations within the junction temperature specification. Semiconductor devices will operate normally as long as the temperature does not exceed an upper limit specified as the ambient temperature and the temperature of the junctions inside the semiconductor. If this upper limit is exceeded then the semiconductor stops working and operating normally and will be damaged. Thermal management is indispensable when using the FPGA for high-power applications or using it under high operating temperature. The concept of thermal resistance is used when considering heat dissipation. The basis for a power design methodology is based on the thermal device specs published in the respective datasheet. So for example, on the ECP2/M device datasheet, you'll find tJCOM and tJIND in the absolutely maximum rating section of the datasheet. While total power, ambient temperature, thermal resistance, and airflow all contribute to device thermal dynamics, the junction temperature tJ is key to reliable device operation. You should also be aware of the min/max numbers for supply voltages, since they may help you reduce static power.

So to avoid reliability issues, semiconductor vendors specify a maximum allowable junction temperature in the datasheet that we've seen. You should always complete a thermal analysis of your design to ensure the device and the package don't exceed the junction temperature requirements. The internal data shown is relative, and the actual values depend on a variety of factors like die size, paddle size, airflow, power supplied, the PCB design itself, and, of course, the user application data there will superseded the package thermal data provided by the device vendor. The most common examples are θJA, thermal resistance junction-to-ambient, θJC, thermal resistance junction-to-case, and a common other factor is θJB, the thermal resistance junction-to-board. The maximum junction temperature of the device is going to be calculated by these expressions: TJ is TA plus the product of power times θJA. We use the total power consumption of the device, and θJA is commonly used with natural or forced convection air-cooled systems, and θJC is useful when you're considering that the package has a high conductivity case mounted directly to the PCB or a heatsink.

This chart illustrates the thermal resistance, θJA and θJC characteristics across the package range of the ECP2/M family. It demonstrates the benefits of certain package types and airflow. When designing a system, designers much make sure that the devices will operate at specified temperatures within the system environment. This is particular important to consider before a system is designed. The ability the estimate the device's operating temperature prior to board design also allows the designer to better plan for budgeting and airflow. A commercial device is likely to show speed degradation in a junction temperature above 85 degrees C, and an industrial device at over 100 degrees C. It's required that the device temperature be kept below these limits to achieve your guaranteed speed operation.

Static or DC power reduction tips include using a sleep mode if it's available. For example, during a period of system activity with the LatticeXP device, they can be placed on a sleep mode. And during this mode standby current is reduced by over one thousand times. The power supplies don't have to be switched. Another technique is to reduce your operating voltage obviously to look at the specs for VCC and VCCJ at the lower end the device specification. Also, clearly minimizing the operating temperature can be counted for by using packages with a lower thermal impedance.

Read also: Power Saving Design Techniques with Low Cost FPGAs 2/2