One of these traps refers to the stability of the output voltage, which is something the designer tends to take for granted. The general philosophy is that you only need to add a low ESR output capacitor, maybe an input capacitor (if the datasheet says so) and there you go: you power supply is finished!

This was not a bad approach, and it would work fine when the output capacitor would generally be a tantalum. Lately, however, large value ceramic capacitors emerged on the market in smaller and smaller packages. These are tempting for the designer, especially because of their low price and small footprint. So many new applications use a simple ceramic as the bulk output capacitor. What is different from the tantalum ones is not only the size, but also the ESR (Equivalent Series Resistance). And due to the nature of the linear voltage regulator, it can have a negative impact on the output stability of the voltage. The theory behind the explanation is quite mathematical, but we’ll try and explain it in as simple terms of possible.
The simplified diagram of a Low Drop Regulator and external components may be seen below:

To understand where the instability is coming from, the circuit needs to be regarded as a system. System theory says that a feedback system is stable as long as it has sufficient phase margin (amongst others). When plotting the gain and phase of the regulator circuit, one should take into account the two poles introduced by the PNP transistor (which is seen as a Pass Element) and by the Error Amplifier. The load resistance together with the bulk capacitor on the output creates a third pole which also needs to be represented in the plots.
To prevent the system from oscillating, one must ensure a phase margin of at least 30:

Due to the positioning of the poles and zeroes on the frequency axis, it is possible to end up in a situation like the one below, where the phase margin falls below 0 and the system thus becomes unstable.

To prevent this, the poles/zeroes should be adjusted so that one of them becomes dominant (is shifted to low frequencies) and causing the system gain to fall below zero before the next parasitic pole is reached. The only elements through which the poles can be adjusted are the integrated compensation resistor Rc, the integrated compensation capacitor Cc in tandem with the integrated output impedance of the error amplifier Zc, and the output capacitor which can influence the dominant pole together with the load resistance. Out of these, it is only the output capacitor with its ESR that is under the control of the power supply designer. A smart approach would tweak these values so that the system is given enough phase margin to be considered stable. When implementing the design, one has to take into account how the current consumption of the load resistance and the output capacitor influence the plots. Complicated mathematical calculations would prove a point, but we are more interested in the practical aspect of the problem.




Practical aspect
The bottom line is that you can get a simple linear voltage regulator circuit with unstable output. How? Just by using a ceramic output capacitor which has a very low ESR. Traditionally, the minimum ESR value for stable operation is not mentioned in the datasheets of the regulators, as its value is so low that it would never be achieved with tantalum and aluminum capacitors. So only the maximum ESR value is specified but too large ESR is a common known problem and designers usually look for it in the datasheet.
It can happened, however, that for very small current consumptions from the load, if the ESR is too small, the system will also start to oscillate based on the theory briefly mentioned above. Therefore, more and more datasheets include now a graph indicating the ESR output stability range. For the TLE4274, for instance (from Infineon) it looks like this:

The interpretation of the graph is as follows: if the load draws less than 400uA from the supply, then at least 1Ohm ESR is required from the output bulk capacitor. This is somewhat contrary to the general practice where the designer strives to put the biggest (though cheapest) capacitor value with the smallest ESR.
Therefore, care should be exercised when selecting the output capacitor. Generally with tantalum and aluminum the danger is that the ESR would be too high. However, the value of the resistance is thoroughly documented in their datasheets and the engineer can match it to what the voltage regulator needs. Unfortunately, we cannot say the same about ceramics. Their ESR is generally so low (and their manufacturers strived to make it as low as possible to get the “perfect cap”) that in the vast majority of ceramic capacitor datasheets it is not even mentioned. In such circumstances, you should avoid over dimensioning the output capacitor in terms of uF value.