The SPI Initialization
The SPI module initialization it's happen in these two simples instructions:

 void encInit(){
  	TRISB = 0xFF;		// configuration I/O di PORTB
  	TRISC = 0xD1;		// configuration I/O di PORTC
  	PORTC = 0x00;
	
	SSPSTAT = 0x40;	
	SSPCON1 = 0x20;

In particular the module MSSP is enabled and configured in "0,0"modality, with clock equivalent at Fosc/4.

ENC28J60 Initialization
The controller initialization predicts the various registers configurations, as well as the qualification to the reception.

#define RX_BUF_START	0
#define RX_BUF_END	6499	
#define	TX_BUF_START	6500
 ....
setBank(0);
writeReg(ERXSTL,   LOW(RX_BUF_START));		//
writeReg(ERXSTH,   HIGH(RX_BUF_START));		// start buffer of the reading
writeReg(ERXRDPTL, LOW(RX_BUF_END));		//
writeReg(ERXRDPTH, HIGH(RX_BUF_END));		//  buffer punter of the reading
writeReg(ERXNDL,   LOW(RX_BUF_END));		//
writeReg(ERXNDH,   HIGH(RX_BUF_END));		// fine buffer of the reading
writeReg(ETXSTL,   LOW(TX_BUF_START));		//
writeReg(ETXSTH,   HIGH(TX_BUF_START));		// start buffer of the reading

The ENC28J60 buffer can be divided between the transmission memory and the reception.
To do that already si configurano i puntatori del buffer di ricezione; the memory remaining will be the transmission buffer.
The registers ERXST contain the first byte address of the reception buffer, while the ERXND registers the last byte.
In ERXRDPT, instead, resides the reading punter of RX memory, or rather check off a zone (together with ERXWRPT) which must be elaborated from the PIC and so can't be wrote; initially the value of this address is the same with ERXND (must be odd aster a problem described in Errata). The ERXWRPT register is zero at reset and is updated automatically to a packet reception.

setBank(2);
writeReg(MACON1, 0b01101);  		// MARXEN,  TXPAUS,  RXPAUS
writeReg(MACON3, 0b00110000); 		// Half Duplex, Padding 60byte, CRC
writeReg(MAIPGL, 0x12); 		//
writeReg(MAIPGH, 0x0C); 		//
writeReg(MABBIPG,0x12); 		// Inter-Packet Gap

These registers configure the MAC module.Through the MACON1 register is enabled the MAC module and the pause plot reception/transmission.
With the MACON3 register is choice the Duplex (Half or Full) modality of the MAC module that must be imposted in the same mode in the PHY module too; also in this register there are presentes some configurations about Padding automatic and the CRC calculation.
The MAIPG and MABBIPG registers contain the pause values between the packets; those presents in the code are the standard values.

writeReg(MAMXFLL, LOW(1500));
writeReg(MAMXFLH, HIGH(1500));

In the MAXFL (Max Frame Length) registers is salved the maximum dimension allowed for a packet; the controller can be configured that refuses to send a packet which pass this limit.

#define MY_MAC1     0x00
#define MY_MAC2     0x04
#define MY_MAC3     0xA3
#define MY_MAC4     0x00
#define MY_MAC5     0x00
#define MY_MAC6     0x00
  ....
setBank(3);
writeReg(MAADR1, MY_MAC1);
writeReg(MAADR2, MY_MAC2);
writeReg(MAADR3, MY_MAC3);
writeReg(MAADR4, MY_MAC4);
writeReg(MAADR5, MY_MAC5);
writeReg(MAADR6, MY_MAC6);

The MAC address of our device is saved in the MACADR registers; these are used from the filter to reject the packets which aren't destined to the controller, so the address isn't insert automatically in the send packets.

writePHY(PHCON2, 0b0000000100000000);	// disability the loopback
writePHY(PHCON1, 0);			// ability the PHY

setBank(1);
writeReg(ERXFCON, 0b10100001); 		// impost the reception filters
BFSReg(ECON1, 0b100);         		// ability the reception

With this last fragment ends the controller initialization. The PHY module hasn't many options to configure, the only options to configure are the LoopBack disabling (used to make the test) and the module qualification.
The filters are setts to accept just the packets for the configured MAC address and broadcast.