The ENC28J60 controller
The ENC28J60 Microchip is a Ethernet 10Base-T (10Mbps duplicated) controller, sticking to the IEEE 802.3 standard.
It is constituted from a PHY (physical level) module, a MAC (MAC under level) module, a 8byte RAM memory to take in the packets in reception and in transmission and a module for the serial SPI communication
The chip has just 28pin and needs a few externals components, that's why can be simply inserted in any project.

Revisions and Errata
The ENC28J60, like each chip from Microchip, has a revision number (REVID), so each chip with a certain REVID can have some differences compared to a chip with another number.
To know the chip version there two ways: the first is to read an internal register between SPI interface; the second is to ask the Microchip assistance , which can find the REVID between the serial at seven-figure under the chip.
The revision more recent is at B5, and until now is possible to create software and hardware in such way not to concern the review number; the only thing that changes at hardware level is a resistance which we'll see it a little bit later.
Beyond the controller datasheet a very important document is theErrata (relative at each review): here there are presented some chip problemes and relatives solutions, as well as the differences between a review and another.
The hardware
This is the circuit scheme realized by me to write this article.

The ENC28J60 is fueled by a 3.3V (max 180mA) tension, so there are some various possible configurations:

• To fuel all the circuit (PIC included) at 3.3V, can be used a PIC18F25J10 or similar, which can work at 40Mhz also at this tension; others PIC, instead, function just at minors frequency.
• Fueling the PIC at 5V, there are necessary some level adapters (simple logical ports CMOS, 74HC08 type), for the ENC exits which go to PIC (SO, CLKOUT, INT, WOL); the controller (CS, SCK, SI, RESET) entrances are tolerant at 5V.
• The PIC, usually, have like threshold value a logical value 1 at entrance of 2V, that's why these level translators would not seem indispensable, like is described in ENC28J60 datasheet , so in my scheme aren't presented.

The controller is projected to work at 25Mhz, that's why is necessary a quartz of this frequency between the OSC1 and OSC2 pins, plus two ceramic condensers connected to the ground. The value of these condensers ins't specified in the datasheet, but I presume is around 15pF.
Can be also used an external clock, connected at OSC1 pic, but it must be very precise (+/- 50ppm).

An important component is RBIAS, its value changes after the chip review: for the B1-B4 review is of 2.7Kohm 1%, while for the B5 is of 2.32K 1%; its value it's important to respect the IEE specifics, that's why is good to be sure that you have it (we'll see how).
The datasheet names a "ferrite bead", but doesn't specify the value: in my scheme I replaced it with an inductance from 1mH.

The last important components are the RJ45 connector and the relatives filters (Magnetics): there are connectors with the filters integrated, or connector and filters apart.
In my case I used a connector ERNI with the filters integrated (attention to the scheme, the pin could be various from another connector type).
In each case is indispensable to follow with attention the scheme presented in the datasheet, which I return it followed (the transformers 1:1 are the Filters):

The Magnetics are some little black cases which can recover (with the connector) from the network card.

About hardware:
- The INT (interrupt) pin isn't used by the software, that's why if you don't intend to exploit the interruption can be not connect.
- The ENC28J60 has between its characteristics theauto-polarity, or rather the pin TPIN+ and TPIN-, even reversed, function the same; in fact it isn't true (the problem is described in the Errata), so is advisable an accurate control of these pins in circuit planning/montage phase
- The datasheet advises to insert ceramic condensers from 0.1uF, for every couple of Vcc-Vss pins.

Organization of the Memory
The chip memory is divided in two parts: the rx/tx buffer and the control registers. To the both it is approached through the SPI interface.
The buffer is a dual port RAM, configurable to be able to divide it to your taste, between the reception memory and the transmission one.
The control registers structure resumes that one already present in the PIC: this is constituted from a registers series at 8bit, divided in frames, through is possible to configure the device.
These are divided in registers ETH, MAC, MII and PHY; the first three are found in the benches of registries, while registries PHY it is approached through registries MII.

We will see the function of several registries as we will make use of it.