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In this configuration, the dsPIC (R) DSC is configured to provide its maximum computational power. To do that, the internal PLL is used to push the internal frequency Fosc to 80 MHz. As a consequence, Fcy become 40 MHz, which is the nominal maximum computational power of 40 MIPS declared by Microchip. In this case, the tick duration is 25 ns.
To configure the system in this way, the C language has to contain the following compiler directive:
_FOSCSEL ( FNOSC_PRIPLL);
Moreover, at the beginning of the main function, the PLL multiplier registers needs to be set with the following code:
/* Clock setup for 40 MIPS */
CLKDIVbits. DOZEN = 0;
CLKDIVbits. PLLPRE = 0;
CLKDIVbits. PLLPOST = 0;
PLLFBDbits. PLLDIV = 78;
/* Wait for PLL to lock */
while( OSCCONbits. LOCK !=1);
Finally, the OIL file will contain the following line:
KERNEL_TYPE = EDF { TICK_TIME = "25 ns ";};
The maximum relative deadline which can be expressed in the OIL file is 25ns  231,
which is slightly more than 53 secs.