Espanol
The code generated by the Scilab/Scicos code generator for FLEX uses the template named pic30_empty_scicos, and has the following symplifing assumptions:
1. There is a single sampling time Ts in the system;
2. Ts is forced to 1 ms;
3. Every sampling time specified by the user under the Scicos design will be rounded to a multiple of a millisecond;
4. An Erika Enterprise counter is linked to the a periodic timer;
5. The periodic timer used in the dsPIC hardware is set to raise an interrupt every 1 ms;
6. An Erika Enterprise alarm is attached to the counter, to periodically activate a task;
7. The task body just calls the routines generated by the Scicos code generator. Which executes the functions you specified in the design;
8. The PWM object has a fixed period of 1 ms. This means that if the sampling period is a multiple of Ts, then the PWM will repeat the same duty cycle until the PWN value is changed;
9. The A/D converter always works “on demand”, meaning it always executes the following steps:
• selects a channel;
• starts the conversion;
• waits for the end of the conversion (typically max 10μsec)
• it converts the result in a value from 0.0V and 3.3V
10. To speedup the compilation process, the default configuration does not produce the dependency files and the .src file from every .c file.
|
French
Italian
