MAX3670 - Basic Description

The MAX3670 is a clock generator IC that is low-jitter 155MHz/622MHz reference designed for system clock distribution and frequency synchronization in OC-48 and OC-192 SONET/SDH and WDM transmission systems. The MAX3670 contains a phase/frequency detector, an operational amplifier (op amp), prescaler dividers and input/output buffers. With the aid of an external VCO, the MAX3670 can be configured easily as a PLL with bandwidth programmable from 15Hz to 20kHz. The MAX3670 operates from a single +3.3V or +5.0V supply, and dissipates 150mW (typ) at 3.3V. The operating temperature range is from -40°C to +85°C. The chip is available in a 5mm ✕ 5mm, 32-pin QFN package.

Detailed Description - MAX3670

The MAX3670 contains all the blocks needed to form a PLL except for the VCO, which must be supplied separately. The MAX3670 consists of input buffers for the reference clock and VCO, input and output clock-divider circuitry, LOL detection circuitry, gain-control logic, a phase-frequency detector and charge pump, an op amp, and PECL output buffers. This device is designed to clean up the noise on the reference clock input and provide a low-jitter system clock output.

Input Buffer for Reference:
Clock and VCO The MAX3670 contains differential inputs for the reference clock and the VCO. These inputs can be DC-coupled and are internally biased with high impedance so that they can be AC-coupled (Figure 1 in the Interface Schematic section). A single-ended VCO or reference clock can also be applied. Input and Output Clock-Divider Circuitry The reference clock and VCO input buffers are followed by a pair of clock dividers that prescale the input frequency of the reference clock and VCO to 77.76MHz. Depending on the input clock frequency of 77.76MHz,
155.52MHz, or 622.08MHz, the clock divider ratio must be set to 1, 2, or 8, respectively. The POUT output buffer is preceded by a clock divider that scales the main clock output by 1, 2, 4, or 8 to provide an optional clock.

LOL Detection Circuitry:
The MAX3670 incorporates a loss-of-lock (LOL) monitor that consists of an XOR gate, filter, and comparator with adjustable threshold (see “LOL Setup” in the Applications section). A loss-of-lock condition is signaled with a TTL low when the reference clock frequency differs from the VCO frequency. Gain-Control Logic The gain-control circuitry facilitates the tuning of the loop bandwidth by setting phase-detector gain and frequency-divider ratio. The gain-control logic can be programmed to divide from 1 to 1024, in binary multiples, and to adjust the phase detector gain to 5μA/UI or 20μA/UI (see Table 3 in Setting the Loop Bandwidth section).

Applications

-OC-12 to OC-192 SONET/WDM Transport Systems
-Clock Jitter Clean-Up and Frequency Synchronization
-Frequency Conversion System Clock Distribution

Features
- Single +3.3V or +5.0V Supply
- Power Dissipation: 150mW at +3.3V Supply
- External VCO Center Frequencies (fVCO): 155MHz to 670MHz
- Reference Clock Frequencies: fVCO, fVCO/2, fVCO/8
- Main Clock Output Frequency: fVCO
- Optional Output Clock Frequencies: fVCO, fVCO/2, fVCO/4, fVCO/8
- Low Intrinsic Jitter: < 0.4psRMS
- Loss-of-Lock Indicator
- PECL Clock Output Interface

MAX3670