Lattice Semiconductor launched the 40 Gbps SERDES Framer Interface, Level 5 (SFI5) Intellectual Property (IP) Core in the LatticeSC and LatticeSCM FPGA families. The solution utilizes 17 SERDES (SERializer/DESerializer) channels in the LatticeSC/M devices - including the Lattice SFI5 soft IP core, and enables flexible and high performance next generation 40 Gbps systems.

The LatticeSCM family provides:

5 logic density points between 15K and 115K LUTs
4- to 32-channels of embedded SERDES
embedded memory capacity from 1 to 7.8

Lattice's unique MACO embedded structured ASIC blocks are available on LatticeSCM FPGA devices and deliver pre-engineered, standard-compliant IP functions developed by Lattice to shorten end-system time to market. The LatticeSC/M families of FPGAs are supported by Lattice's latest generation of design tools, the ispLEVER version 7.2 software design tool suite.

Megabits of dual-port block RAM and general-purpose 2 Gbps PURESPEED I/O ranging from 139 to 942 I/Os. Each device also features 8 analog PLLs and 12 digital DLLs and ample clock routing for optimum clock flexibility. The SFI5 IP solution is available as a downloadable core from the Lattice Semiconductor website.

Read more: http://www.latticesemi.com/corporate/newscenter/productnews/2009/r090120...