Latch-Up Protection For MOSFET Drivers

Most of the CMOS ICs, when in proper condition, can “latch” just like an SCR, thus creating a short circuit from the positive supply voltage to ground. To prevent latch-up you have to properly decouple IC, Clamp outputs with diodes when driving inductive loads, Clamp inputs with diodes if input signal exceeds the negative or positive rails of the power supply and Use star grounds, if at all possible, in highcurrent applications.

In fabricating CMOS ICs, parasitic bipolar transistors are formed as a by-product of the CMOS process. These transistors are inherent in the CMOS structure and can't be eliminated. The P-channel device has a parasitic PNP and the N-channel has a parasitic NPN. Through internal connections, the two parasitics form a four-layer SCR structure .

The parasitic SCR can be turned on if the P+ of the Pchannel drain is raised above VS+. This action will bias the drain P+ of parasitic Q1 (Q1's emitter), back through Q1's base and return to VS+ through bulk resistance R1. A similar situation can occur if the drain of the N-channel MOSFET (emitter of Q2) is taken below the VS- supply.

This emitter base junction of the parasitic bipolar is the parasitic diode that is also found in power MOSFETs. One of these diodes exists in every CMOS structure for both N- and P-channel devices. This corresponds with the fact that there exists a parasitic bipolar for every MOSFET in the IC, including the input transistors. Turn any one of them on and the SCR action will occur. In most applications, the triggering of the parasitic SCR results in the destruction of the IC. The only time destruction does not occur is when the supply current to the device is limited. In this case, the device will resume normal operation when the parasitic SCR is unlatched by cycling the supply current through zero.

Clean grounds are important in any system, but they are especially important in analog and power processing circuits, becoming even more critical when CMOS ICs are used.

Ripple and noise on the power supply voltage is another source of latch-up problems. VS+ may be properly decoupled at the power supply, but at the supply pins of the IC, voltage transients occur. These transients are generated by the combination of the fast peak currents being drawn by the IC and the parasitic inductances and resistances of the power supply conductors

A very reliable method for preventing parasitic SCR action is to guard all the susceptible IC pins with steering diodes. This is most commonly done when a MOSFET driver is driving an inductive load, such as a long length of wire or a pulse transformer.

In applications where triggering of the parasitic SCR is not a concern and protecting the IC from destruction is the only issue, adding a resistor in series with the power supply pin will prevent device destruction. Once the SCR has been triggered, the supply voltage will have to be brought momentarily to zero to reset the SCR, but no damage will have been done to the IC unless the series resistor was not large enough to limit the fault current to a safe value. This is the lowest cost solution to prevent device damage.

Thus Latch-up in CMOS ICs is preventable.

Latch-Up Protection For MOSFET Drivers