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Introduction to the UNI/O EEPROM Family Part 2 of 2

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Introduction to the UNI_O EEPROM Family Part 2 of 2.jpg

Now that we have reviewed the different buses, I want to spend some time discussing a few of the UNI/O bus requirements. As you already learned the UNI/O bus uses a single I/O port. But let’s discuss what that means.

First only 3 pins are used. Power, ground and a single serial data I/O port. For communications to be supported using a single line, a Manchester encoded communication protocol is used. In a UNI/O bus interface the master will establish the data rate by sending an 8 bit start header at the beginning of all communications and it is the job of the UNI/O slate device to sink up to this data rate. An example of an 8 bit start header is shown below. The slave will begin the synchronization step after it receives a low start header pulse but will synchronize only after 8 consecutive pulses of alternating zeros and ones have been recognized.

We have been talking about Manchester communications. So now I would like to provide an overview of this protocol. The main reason for selecting the Manchester communication protocol was to enable the use of a single signal line for both the clock and data. Since data transitions occur on every bit, the clock can easily be extracted from the data and the UNI/O device can sink to the data rate established by the MCU. As an example, take a look at the diagram below where we are showing the bit period TE. This period will support the UNI/O frequency range and is controlled by the master and the transitions are only valid at the middle of the bit period. A logic high is generated by sending a rising edge in the middle of a bit period and a logic low is generated by sending a falling edge. Any adjustments to the signal can be made at the edge of the bit period since the middle of the period is reserved for the actual Manchester data.

We have been discussing the UNI/O bus. Now let’s talk about the UNI/O EEPROM features. First the connection to an UNI/O device will only need a single I/O port for communication. Since there is not a limitation on the densities, we are first releasing the lower density, 1K, 2K, 4K, 8K and 16K bit devices. A wide voltage range from 1.8 volts to 5.5 volts over a frequency range from 10 KHz to a 100 KHz will be supported. This includes the resynchronization circuitry that allows the UNI/O slave device to sink up in frequency and phase to any MCU master. We are now able to support a 3 lead SAT23 package with the standard 8 lead SOIC MSOP, 2/3 TDFN and PDIP packages are also supported. With only a single connection available the UNI/O protocol is designed to be software addressable like the I squared C bus and has software right protect that operates like the SPI bus block protect. In order to support any type of application, both industrial and extended temperatures are supported. And to help you get started with development, we have the MPLAB starter kit for serial memory product.

Even though the UNI/O family is new, we have identified a few applications where this type of memory can be used. Of course there will be many more applications in the future but that’s up to you. For applications where authentication is required we know that the UNI/O devices can be used in printer cartridges or batteries. In applications where calibration parameters need to be stored, the limited I/O is very useful in medical applications like glucose drips or insulin pumps. If identification is a requirement, PC cards can also use the UNI/O device or the enumeration memory. Where cabling is an issue and you have data logging requirement, the single signal line is definitely an advantage.

If you are as exited about the UNI/O product line as we are, but don’t have a platform to evaluate an entirely new bus protocol, we may have an answer for you. First let’s take look at the pin outs of the UNI/O EEPROM in an 8 lead package. In either of the SOIC, MSOP, TDFN or PDIP packages, only 3 pins, VCC, VSS and SEIO are used and 5 no connect pins are also used. Let’s take a look at the pin out for an I squared C EEPROM in the same package.

As you can see, the VCC, VSS and data lines use the same pins as the UNI/O EEPROM. The pin out for an SPI EEPROM also uses the same pins, VCC, VSS and the data input signal. What this means is that you can un sorter your existing I squared C or SPI EEPROM devices and replace it with the UNI/O device for a very easy evaluation. Microchip even includes the software drivers for popular micro controllers that are in use today. Please check our webpage for available drivers or drivers currently in process.

For more information about UNI/O EEPRPOMs, check out our website. Our datasheets are an excellent source of information and not only provide information on our new UNI/O EEPROM family but they describe in great detail how the UNI/O bus operates. We also have several educational app notes that should provide more information. Between the application notes and the product data sheets, you should have enough information to help you understand this new bus standard and how the UNI/O devices will operate in your system. This includes our recommended design practices for this new family.

Finally we have a list of the current software drivers available on our website and those that are in process. You can also check out the UNI/O web forum page for additional information from other designers.
Watch & Read: Introduction to the UNI/O EEPROM Family Part 1 of 2

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