Our cars are media rooms on four wheels. The technology changed the meaning of "road trip". We have GPS-based Navigation systems and passenger entertainment with wireless connectivity to portable media players, cell phones and laptops. If we add voice response then we have the ability to control all of these devices without taking our hands off the steering wheel. All of these functionalities require an integrated circuit with the ability to drive the entire system. That's why Freescale developed i.MX35 - the multimedia applications processor for automotive.
i.MX35x - A new multimedia processor for automotive infotainment video-enabled applications
The i.MX35x products launch Freescale’s ARM11 portfolio into industrial applications by providing the product features, product quality, industrial pitch and device longevity required by customers.
Portable Navigation Devices
Factory control, metering
Home graphical panels
The i.MX35x product development kit provides customers the value add hardware reference design and software source code they need in order to minimize their time to market and development costs.
ARM11 running at 532 MHz, with L2 cache and VFP
Large integrated SRAM (128KB) for improved system performance
LCD controller for up to SVGA resolution
Open VG 1.1 support for accelerating Adobe Flash applications
Multiple boot options including USB and SD
USB Host and OTG controllers with integrated PHYs
Industrial connectivity, including Ethernet and CAN
Flexible memory support for mDDR, DDR2, SDRAM, and SLC/MLC NAND
Software packages for Linux and Windows Embedded CE 6.0 provided and supported by Freescale, complete with ARM11 multimedia codecs.
Support for DDR2 memories which can provide customer system cost savings.
Support for larger pitch packages that contribute to lower manufacturing costs.
Real 2D Accelerator to enable advanced 2.5D UI at lower cost than 3D HW accelerator
The i.MX35 is a low-tier implementation of i.MX31 addressing the automobile infotainment video-enabled audio-player market. The iMX35 platform is intended to support the following:
• External connectivity via Bluetooth
• Multi-standard audio playback
• Multi-standard video playback of 30fps at QVGA (320x240) resolution
• Open OS support (Linux, WinCE, QNX, other auto RTOS)
The iMX35 is partitioned into two major subsystems: the ARM1136 platform, and the SDMA platform with external memory interface (EMI).
The IMX35 ARM1136 Platform is based on the ARM1136 platform. The ARM1136 Platform has the following features:
• ARM1136JF-S processor
• 16-Kbyte level-one (L1) instruction cache
• 16-Kbyte L1 data cache
• 128-Kbyte level-two (L2) cache
• Vector floating point unit (VFP11)
• Maximum frequency of the core (including VFP11), L1, and L2 caches is:
- — 400 MHz at 1.2 V minimum
— 532 MHz at 1.55 V minimum
To boost the multimedia performance, the following hardware accelerators are integrated:
• Image processing unit (IPU)
• 2-D graphics accelerator
Security functions are enabled and accelerated by the following hardware:
• Secure JTAG controller (SJC). Protects JTAG from debug port attacks by regulating or blocking
access to the system debug features
• Real-time integrity checker type2 (RTICv3). RTIC type1, enhanced with SHA-256 engine
• Secure RAM module and security monitor (SCC), providing 2 Kbytes of secure storage of
sensitive information in both on-chip and off-chip RAM, non-volatile memory
• High assurance boot (HAB) with SHA-256
• Random number generator controller (RNGC) capable of generating 32-bit random numbers
The memory system consists of the following levels:
• Level-1 cache
— Instruction (16 Kbytes)
— Data (16 Kbytes)
• Level-2 cache
- — Unified instruction and data (128 Kbytes)
• Level-2 memory
- — Boot ROM, including HAB (32 Kbytes)
— Internal SRAM (128 Kbytes)
— Secure RAM (2 Kbytes)
iMX35 is built around the following system buses:
• 64-bit AMBA AHB 2.0 (AHB-64)—Used by most of the high bandwidth bus master peripherals, such as IPU and GPU2D.
• 32-bit AMBA AHB 2.0 (AHB)—Used by most of the bus master peripherals, such as SDMA, RTICv3, USB, EMI, and so forth; see the block diagram for the complete list.
• 32-bit IP bus—Used for control (and slow data traffic) of most of the SoC peripheral devices. iMX35 enables the following interfaces to external devices:
• Two CAN interfaces
• One CE-ATA interface
• Two SDIO 2.0/MMC 4.2 interfaces (up to 416 Mbps each)
• Two CSPI (up to 52 Mbps each)
• DDR2 and 32 bit SDRAM (up to 133 MHz)
• Enhanced serial audio interface (ESAI)
• Ethernet 10/100 Mbps
• Flash controller—MLC/SLC, NAND, and NOR
• GPIO with interrupt capabilities
• Three I2C (up to 400 Kbps each)
• Secure JTAG
• Keypad port
• Memory stick/Pro
• Media local bus (MLB) interface
• 1-Wire module
• Parallel camera sensor (4/8/10/16-bit data port for video color models YCC, YU
• Parallel display (primary up to 24-bit, 1024 x 1024)
• P-ATA (up to 66 MBytes/s)
• S/PDIF transceiver
• Two SSIs
• Three UARTs (up to 4.0 Mbps each)
• One USB 2.0 Host (up to 480 Mbps) with FS PHY
• One USB 2.0 OTG (up to 480 Mbps) controller with HS OTG PHY
The MCIMX35 consists of the following major subsystems:
- • ARM1136 Platform
• SDMA Platform and EMI
1. ARM1136 Platform Overview
The ARM1136 platform is responsible for running the operating system and applications software, providing the user interface, and supplying access to integrated and external peripherals. The look and feel of the product depends on the software running on this processor, ultimately tying market acceptance to the availability of a wide variety of off-the-shelf, third-party software and development tools. Over the past couple of years, the ARM CPU family has emerged as the de facto standard for mobile application processors. To leverage this growing software base, the ARM1136 platform is based on the ARM architecture. With high-frequency operation and coupled with an L2 cache, the ARM1136 platform achieves multimedia and graphics performance to meet the targets for this market. The ARM1136 platform is built around an ARM1136JF-S core with 16-Kbyte instruction and 16-Kbyte data L1 caches, an MMU, a 128-Kbyte L2 cache, a multi-ported crossbar switch, and advanced debug and trace interfaces. The ARM11 core is intended to operate at a maximum frequency of 532 MHz in order to support the required multimedia use cases, such as concurrent video playback CIF at 30 fps and MP3 audio decode. Furthermore, an image processing unit is integrated into the ARM1136 platform to offload the ARM11 core from performing functions such as color-space conversion, image rotation and scaling, graphics overlay, and pre- and post-processing. Peripheral functionality belonging to the ARM1136 platform include the user interface, connectivity, display, security, and memory interfaces and 128 Kbytes of multipurpose SRAM. This SRAM can be used as audio RAM, scratch-pad RAM by the ARM11, or it can be accessed by the IPU for use as a display buffer for partial display refresh during deep sleep mode (DSM).
2. SDMA Platform and EMI Overview
The SDMA platform is composed of the SDMA peripherals, a Smart DMA Engine (SDMA), and a number of miscellaneous modules. For maximum flexibility, some peripherals are directly accessible by the
SDMA engine. The external memory subsystem represents a significant investment in chipset cost and board area. High-performance processors such as the ARM11 require a significant amount of bus bandwidth to achieve their maximum potential. The challenge here is to maximize the performance while minimizing the bandwidth. To achieve that, the iMX35 includes a hierarchical memory architecture including L1 caches, unified L2 cache and M2 memory. This reduces the bandwidth demands for the external bus and external memory. The external memory subsystem supports a flexible external memory system, including support for SDRAM (SDR and DDR), and NAND flash.
3. Advanced Power Management Overview
To address the continuing need to reduce power consumption, the following techniques have been incorporated into the iMX35 processor:
• Clock gating
• Power gating
• Power-optimized synthesis
• Well biasing
• Dynamic process and temperature compensation (DPTC)
• Dynamic voltage and frequency scaling (DVFS)
By inserting gating into the clock paths, unused portions of the chip can be disabled. Since static CMOS logic consumes only leakage power, significant power savings can be realized. iMX35 clock gating is inserted both manually on a large functional block basis and automatically within the blocks during logic synthesis. Synthesis tools are not only capable of inserting clock gates automatically, but they can also be instructed to minimize power consumption of logic through gate substitution and rearranging of terms to minimize unnecessary transitions. iMX35 integrates both clock gating and power optimization into the synthesis design flow. Well biasing is applying a voltage that is greater than Vdd to the nwells and lower than Vss to the pwells. The effect of applying this well back-bias voltage is to reduce the subthreshold channel leakage. For the 90 nm digital process, it is estimated that the subthreshold leakage will be reduced by a factor of 10 over the nominal leakage. Additionally, the supply voltage for internal logic can be reduced from 1.4 V to 1.2 V to 1.0 V during periods of inactivity.
For further information: i.MX35 Product Summary
Read the Italian version: Con l'i.MX35X l'intrattenimento è on-the-go
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