Implement Advanced Functions in JTAG

JTAG interface adapter3

When a complex PCB has been manufactured, it needs to be tested for functionality. However, a testing that needs to be done prior to the functional tests is ensuring major devices are functional. In-circuit testing used to take care of that in the early days of digital systems. This used to be nearly full-functional testing of individual chips sitting on the PCB. As complexity grew this became nearly impossible in terms of time taken and the test resources costs.

1. Introduction

The integrated-circuits integrated major parts of logic for implementing a system and was using increasing number of transistors. It was a short step for a concept that with such large number of transistors sitting on a chip, some amount of testing logic can be included. Such test controllers can be commanded from outside the chip to conduct internal tests and send out the test results. The additional transistors required will hardly be an overhead. A serial daisy chain then can connect these devices and the IC chips can be tested out one after another and the test results monitored at the edge of the PCB to determine if the board is generally functional. This is the basic concept of the JTAG scheme of testing.

2. JTAG Standards

IEEE 1149.1, IEEE 1149.4 and IEEE 1149.6 are the relevant standards that apply. IEEE 1149.1 is the original standard released in 1990 ( known as the dot1 standard) and updated twice since then. This was primarily for digital circuits. IEEE 1149.4 (the dot4 standard) released in 2000 takes care of analog boundary scan. Digital systems use LVDS (low voltage differential signaling) signal paths for high speed systems increasingly now. The IEEE 1149.6 governs such testing. IEEE 1532 sets up a standard for programming PLD and FPGA devices so that they can be programmed for configuration changes through the JTAG inputs. The IEEE 1149.1 standard defines the embedded test technology in thousands of ICs, provides the test and programming backbone of large number of system designs. A Test Access Port or TAP, a sequential machine , a instruction register and number of data registers need to be implemented in an IC so that it can be tested through the boundary scan arrangement. Boundary Scan Description language (BSDL) defines the syntax that describes how to implement the TAP controller and the operations it should perform.
The IEEE1149.4 or the dot4 specification introduces features that let you test analog signals. AT1, an analog drive pin and AT2, an analog sense pin are introduced. These are connected to internal analog test buses that let you drive and then sense response of analog pieces of function on the IC. IEEE 1149.6 introduces way and means to test the LVDS and capacitively coupled signals. You can send and receive data over such signal paths to detect problems like open pin, shorted pin to ground, open capacitor by the response to the data pulses. A related standard IEEE 1532 deals with standard methods of programming field programmable devices like PLD and FPGA. 1149.1 has been used in manufacturing these devices and the JTAG port have been used for programming these devices. However, there are variations in the way these devices are programmed and that needed a standardization effort. When a device is standard compliant, you could configure, read back data, erase and verify irrespective of the manufacturer. A BSDL description of the uniform algorithm to be used is available in the standard. BSDL is a subset of VHDL language.
Some future standards that are in the works are the IEEE 1149.7 often known as the reduced pin count JTAG, P1581, a standard like the 1532 but for testing of memory devices and SJTAG, an extension for system level testing.

3. JTAG Concepts

JTAG provides access to interconnected digital cells on an IC, provides a method of access for test and diagnostics and software debug. JTAG also gives you a means of in-circuit upgrade and remote firmware upgrade. Fig 1 illustrates the logical supports ICs will need to have inside to support the IEEE 1149.1 standard. Internal cells are serially connected as far as testing arrangement is concerned, as shown in the diagram of figure 1.

device architecture

Figure 1: Logical supports ICs for the IEEE 1149.1 standard.

TMS, TCK and TRST are common signals to all the devices to be included in the test loop. Test serial line is the connected to the TDI (Test data in) line and the results come out of the TDO (Test data out) pin on each device. Devices are supposed to be daisy chained by connecting the TDO line of the first device to TDI of the next device, creating a serial chain. TMS is the test mode select signal; TCK is the test clock that clocks in serial data and TMS signals. TRST* is an asynchronous reset signal. TDI is serially connected to internal blocks as shown. If necessary the test signal can be by passed. For testing analog signals an IC need to have additional facility internally. Test bus interface circuitry needs to take care of combining the digital and analog test paths suitably. The Test bus interface circuit manages the testing based on AT1 inputs and sends out results on the AT2 line. These serial lines are then daisy chained in same fashion as the TDI and TDO lines.

4. Complexities of Serial Daisy Chaining

With a fairly complex board serial testing line will need to be taken through many devices on a PCB. The testing can become a time consuming affair and testing at full rate also can become difficult (Figure 2).

Fig_4

Figure 2: Typical board arrangement

With many different kinds of chips on the board and a large number of devices to be connected in the loop, the testing will become complicated. Only possible solution is if the loop can be broken down into smaller loops. Test programs development also becomes easier to tackle, as you could possibly group devices that are of a similar type as shown in Fig 3.

Fig_5

Figure 3: Partition the loop

You'll need to take this into account while developing the board and include this device and the connections necessary for the testing loops right at the net-list stage. A typical example of the IC that can do this kind of partitioning is the famous SCANSTA 111 and SCANSTA 112. SCANSTA 111 can provide up to 3 partitions while SCANSTA 112 can provide up to seven partitions. For further partitioning one could carry out test sequences of a part of the system with a embedded JTAG test master like SCANSTA 101. This can be controlled by the microprocessor that is driving the sub-system and have the test vectors stored. It can start a test sequence when the higher level test controller asks it to begin testing and then report results to this higher level controller.

Based on text written by DebasisDas
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