In this article, we'll analyze the source of this offset, and then we'll propose a solution based on integrated resistor networks. In precision electronics, amplifier stages must comply with precisely designed performance specifications. One problem encountered when designing these amplifiers is the voltage offset generated by currents flowing into the amplifier inputs.
Before attempting to solve a problem, we need to understand its source. For that purpose, consider the simplified schematic for an ideal op amp.

This simplified schematic depicts an ideal op-amp circuit

To analyze the effect of each of these current sources, assume that VIN = 0V. We assume that the impedance at VIN is small in relation to other impedances, so IBIAS+ will be shunted to ground and have no effect. Because VIN = 0V, V- must also equal 0V. Moreover, because both ends of R1 are at the same 0V potential, it can be eliminated from the analysis. Thus, we immediately see an unwanted output offset (VOUT), due to the input bias current (IBIAS-) and feedback resistor (R2):

The circuit can be improved by adding one extra resistor. We need to examine the effect of this extra resistor, which causes the positive input to be offset negative by IBIAS+ × R3. You can, therefore, adjust R3 to nullify the effect of bias current into the negative input. It is reasonable, however, to make the approximation that positive and negative input bias currents are the same.
With VIN = 0, you can easily calculate VOUT by noting that we have a voltage adder circuit, i.e., the output voltage is the voltage applied to the positive terminal times the voltage gain, plus an offset due to input current leakage into the negative terminal. Because VIN = 0, any voltage applied to the positive terminal is due to leakage into that terminal, and R3.
Read the Application Note.