This article contains implementation instructions for the DDR2/mDDR interface contained on the TMS320DM35x Digital Media System-on-Chip (DMSoC) device. The approach to specifying interface timing for the DDR2/mDDR interface is quite different than on previous devices.

For the DM35x DDR2/mDDR interface, the approach is to specify compatible DDR2/mDDR devices and provide the PCB routing rule solution directly. TI has performed the simulation and system design work to ensure DDR2/mDDR interface timings are met. This document describes the required routing rules.

The DM35x EVM provides an example of a PCB layout following these routing rules that passes FCC EMI requirements. You can copy the DDR2/mDDR portion of this layout directly, but the intent is to allow enough flexibility in the routing rules to meet other PCB requirements.

The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2/mDDR memory system without the need for a complex timing closure process.

The DM35x also supports JEDEC DDR2/mDDR x8 devices in the dual chip configuration. In this case, one chip supplies the upper byte and the second chip supplies the lower byte. Addresses and most control signals are shared just like regular dual chip memory configurations.