Welcome to the training module on Linear Technology LTC2440 – High Speed Delta Sigma ADC. This training module introduces the internal architecture of the LTC2440, its basic operation and key features.

The LTC2440 is a high speed 24-bit No Latency Delta Sigma ADC with 5ppm INL and 5µV offset. It uses proprietary Delta Sigma architecture enabling variable speed and resolution with no latency. Ten speed/resolution combinations (6.9Hz/ 200nVRMS to 3.5kHz/25µVRMS) are programmed through a simple serial interface. Alternatively, by tying a single pin HIGH or LOW, a fast (880Hz/2µVRMS) or ultralow noise (6.9Hz, 200nVRMS, 50/60Hz rejection) speed/resolution combination can be easily selected. The accuracy (offset, full-scale, linearity, drift) and power dissipation are independent of the speed selected. Since there is no latency, a speed/resolution change may be made between conversions with no degradation in performance. Following each conversion cycle, the LTC2440 automatically enters a low power sleep state. Power dissipation may be reduced by increasing the duration of this sleep state. The LTC2440 communicates through a flexible 3-wire or 4-wire digital interface.

The LTC2440 is a high speed, delta-sigma analog-to-digital converter with an easy to use 4-wire serial interface. The 4-wire interface consists of serial data input (SDI), serial data output (SDO), serial clock (SCK) and chip select (CS). The interface, timing, operation cycle and data out format is compatible with the LTC2410. SDI pin is used to select the speed / resolution of the converter. During the data output period, the SDO pin is used as serial data output. During the Conversion and Sleep periods, this pin is used as the conversion status output. The voltage on the differential analog pins can have any value between GND-0.3V and VCC+0.3V. Within these limits the converter bipolar input range (VIN = IN+ – IN–) extends from –0.5x(VREF) to 0.5x(VREF). Outside this input range the converter produces unique over-range and under-range output codes. The LTC2440 can accept a differential reference voltage from 0.1V to VCC. The LTC2440 performs offset and full-scale calibrations every conversion cycle. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift.

The LTC2440 transmits the conversion results and receives the start of conversion command through a synchronous 2-wire, 3-wire or 4-wire interface. During the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result and program the speed/resolution.

The serial data input (SDI, Pin 7) is used to select the speed/resolution of the LTC2440. A simple 2-speed control is selectable by either driving SDI HIGH or LOW. If SDI is grounded the device outputs data at 880Hz with 21 bits effective resolution. By tying SDI HIGH, the converter enters the ultralow noise mode (200nVRMS) with simultaneous 50/60Hz rejection at 6.9Hz output rate. SDI may also be programmed by a serial input data stream under control of SCK during the data output cycle. One of ten speed/resolution ranges from 6.9Hz/200nVRMS to 3.5kHz/21μVRMS may be selected as shown on the table. The conversion following a new selection is valid and performed at the newly selected speed/resolution.

Initially, the LTC2440 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced below 10μA. The part remains in the sleep state as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. Once CS is pulled LOW, the device begins outputting the conversion result. There is no latency in the conversion result. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK. The data output state is finished once 32-bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion and the cycle repeats.

The LTC2440’s 2-wire, 3-wire or 4-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 2-wire or 3-wire I/O, single cycle conversion and auto-start.

The LTC2440 serial output data stream is 32-bits long. The first 3-bits represent status information indicating the sign and conversion state. The next 24-bits are the conversion result, MSB first. The remaining 5-bits are sub LSBs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. In the case of ultrahigh resolution modes, more than 24 effective bits of performance are possible. Under these conditions, sub LSBs are included in the conversion result and represent useful information beyond the 24-bit level. The third and fourth bit together are also used to indicate an under-range condition or an over-range condition.

During the conversion cycle, the LTC2440 draws 8mA supply current independent of the programmed speed. Once the conversion cycle is completed, the device automatically enters a low power sleep state drawing 8μA. The device remains in this state as long as CS is HIGH and data is not shifted out. By adjusting the duration of the sleep state (hold CS HIGH longer) and the duration of the conversion cycle (programming OSR) the DC power dissipation can be reduced.

One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2440 significantly simplifies antialiasing filter requirements. The LTC2440’s speed/resolution is determined by the over sample ratio (OSR) of the on-chip digital filter. The OSR ranges from 64 for 3.5kHz output rate to 32,768 for 6.9Hz output rate. The value of OSR and the sample rate fS determine the filter characteristics of the device. Since the OSR is typically large (≥64), the digital filter offers excellent rejection of input noise sources and simple.

Programmable gain amplifiers (PGAs) are commonly used in systems where a small input signal (RTD, thermocouple, strain gauge) needs to be applied to a wide input range analog-to-digital converter. The convention is to amplify the sensor output voltage range so that it matches the ADC input range. However, the system performance is dominated by the noise performance of the PGA as well as its offset, full-scale, and linearity performance. PGAs degrade the system performance by introducing added error sources drift, cost and complexity. Eliminating the PGA requires a converter with exceptional offset, linearity, full-scale accuracy, drift, and noise performance. The converter requires enough resolution over its full input range to maintain high resolution within a significantly reduced portion of its input span. This allows system designers to directly interface sensors to the ADC while using a small portion of the overall converter input range. The exceptional noise performance of the LTC2440 allows the user to make one conversion with 500,000 counts and no DC errors for any ±50mV range.

If the ADC can be located physically close to the sensor, it can be directly connected to sensors or other sources with impedances up to 350Ω with no other components required as shown in Figure 1. If longer lead lengths are unavoidable, adding an input capacitor close to the ADC input pins will average the charging pulses and prevent reflections.

Many applications will require buffering, particularly where high impedance sources are involved or where the device being measured is located some distance from the LTC2440. the figure shows a network suitable for coupling the inputs of a LTC2440 to a LTC2051 chopper-stabilized op amp. The 3μV offset and low noise of the LTC2051 make it a good choice for buffering the LTC2440. The LTC2051 is configured to be able to drive the 1μF capacitors at the inputs of the LTC2440. The 1μF capacitors should be located close to the ADC input pins. Here lists 3 items for selecting a suitable amplifier as a buffer.

Running with an external oscillator of 100kHz and the highest resolution (OSR = 32,768), the RMS noise of the LTC2440 is 200nV over a full ±2.5V input range. Six decades of current, in either direction, can be measured accurately through a 1Ω resistor independent of low frequency system noise. The flexible common mode input range enables the LTC2440 to digitize these signals near VDD. The LTC1799 is a precision oscillator which frequency is programmed by a single external resistor.

The LTC2440 offers accuracy, stability, and ease of use that are common to the LTC2400 product family. It combines a programmable OSR digital filter with a high speed analog modulator in order to achieve high speed and accuracy independent of output rate. The LTC2440’s wide range of user programmable speed and resolution combinations makes it flexible enough to fit in a wide variety of applications.

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