Freescale has introduced on the i.MX31 processor family an innovative and powerful technology, called Smart Speed, which is able to deliver fast and power-efficient processing for mobile devices.

Smart Speed technology is based on an architecture featuring true parallelism in mobile device processors, thus allowing higher processing capabilities per cpu cycle. On conventional processor architectures, better performances are obtained increasing the CPU frequency; the drawback of that solution is that power consumption increases, as well. Smart Speed technology, instead, brings more CPU power without augmenting the battery drain.

The usage of mobile computers and handheld devices has increased dramatically in the last years, and, as a result, a new problem has risen: battery life has become too short. The solution to this problem is not so easy. On one hand, improvements on battery capacity are possible, but their benefits come at a slow rate: it has been estimated that, approximately, the improvements are five percent every two years. On the other hand, big efforts are required exploring and delivering new technologies which help mobile devices to be more power efficient. With the Smart Speed technology, Freescale has reimagined the processors architectures, from the transistor level to memory accesses, power-saving modes and software blocks. The result are processors able to deliver longer play time maintaining the level of performance requested by modern mobile devices.

Effective Cycles per instruction (eCPI)

In order to better measure the performance level of mobile devices, the effective cycles per instruction (eCPI) index is adopted. For instance, the i.MX31 and i.MX31L multimedia applications processors (both based on the Smart Speed technology) running at 532 MHz feature an eCPI equivalent to a conventional processor running at 3 GHz, but with a better power consumption. The lower the eCPI, the better the performance of the processor; moreover, that results in longer battery’s life. In a processor based on a general-purpose architecture, eCPI ranges from 1.4 o 1.7; in a processor with an architecture including general-purpose execution units (GEUs) to retrieve data and instructions from memory (such as CISC, RISC, DSP), the eCPI measurement is around 1. In order to have an eCPI value below 1, it is necessary to adopt architectures that use spcecialized execution units (SEUs). SEUs need fewer instruction transfers from memory, are more efficient and require less power than GEUs. For example, a processor based on a SEUs architecture with an eCPI value of 0.3, compared to another processor based on a GEUs architecture with an eCPI value of 1.5, will probably require one fifth of the clock frequency to operate at equal speed.

Smart Speed principles

The Smart Speed technology is based on the following three basic principles:

1. the processor’s performance is determined by the eCPI value: efforts shall be made to reduce this performance index by defining which EUs are needed to make the processor more efficient. Better performances are possible increasing the number of tasks to be performed, not just increasing the clock frequency.
2. promote the parallelism among EUs: even a high number of EUs is not enough, if they are most of their time in a wait state. A single task can be broken down in multiple steps and, by using parallelism, their execution can be scheduled and performed in order to reduce wait periods. Parallelism is not achieved by using common bus architecture, but rather with more efficient bus structure, such as crossbar or mesh structures. Smart Speed technology uses a 6x5 crossbar switch which nearly eliminates wait states. A crossbar switch, infact, creates a point-to-point access between bus masters and slaves: all the items connected on one side (the masters) can communicate with all the items connected on the other side (the slaves), and the transactions can occur simultaneously, thus allowing to reach a high parallelism level. If, for instance, the bus speed is set to 166 MHz, and up to five simultaneous transactions are supported, the crossbar can achieve an overall effective throughput equivalent to 830 MHz
3. use the power supply coming from batteries as a precious source of energy: it shall be used in a smart and efficient way.

The following pictures from Freescale show the energy gap based on system, battery and features without and with, respectively, the Smart Speed technology.

The first image represents the gap between battery (in blue) and capabilities related to a traditional architecture, where performances are improved by increasing the clock speed and using the same battery. The second image, instead, shows the gap for a system based on architecture with a more efficient energy management feature.

The following picture shows how the ever-faster mobile technologies are requiring ever increasing power and battery capabilities: with this trend, traditional power architectures may not be able to satisfy ever power-hungry features requested by the mobile market.

Conclusions

Freescale has added many SEUs to the Mobile eXtreme Convergence (MXC) and i.MX families of processors, in order to decrease the eCPI of the system, for functions such as video pre- and post-processing, video processing, graphics and baseband functions. A proper combination of GEUs and SEUs is able to provide parallelism in the system, closing the energy gap for the capabilities required in mobile consumer devices.

Reference

Freescale Semiconctor

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