As FPGA becomes more and more aggressive to be a programmable system on chip, more and more intelligent properties have been implemented on FPGA devices, including various microprocessors, either in hard-processor or soft-core.

Freescale offers various custom devices for important customers. In order to reduce the cost for SoC customers, Freescale has licensed its PowerPC 440/405 to Xilinx. Additionally, Freescale offers its ColdFire V1 soft-core (CFV1CORE_ALTERA) on Altera Cyclone-III FPGA through IPextreme exclusively, for free-of-charge (no license free, no royalty fee). A free ColdFire processor on a low-cost (3.5~4USD), low-power Cyclone III FPGA gives the clients an ideal solution for both prototyping and production. Furthermore, the clients can turn the newly created SoC into a ColdFire ASIC (microcontroller). The clients can license V1 ColdFire Core as fully-synthesizable RTL source code for $10,000 with royalty for 0.02USD for each microcontroller, still through IPextreme. According to my experience, the price is reasonable for designing a new microcontroller. If you are interested in advanced ColdFire V2, the clients can buy the license from IPextreme as well. 

Features

The small-footprint V1 ColdFire core is designed for entry-level 32-bit applications. It is designed to enhance system utilization resulting in the low-power consumption while giving more than ten times the performance of an 8-bit MCU. ColdFire V1 shares peripheral blocks with S08 family and BDM interface. As a result, ColdFire V1 is pin-to-pin compatible with S08 microcontroller with 32-bit performance.

The CFV1CORE_ALTERA is the (almost) same V1 ColdFire processor core implemented in Freescale’s MCF51QExx devices, but delivered as an Altera SOPC Builder ready design optimized for the Altera Cyclone III FPGA device (3C25). The V1 ColdFire system bus has been adapted to the Altera Avalon system interface for the CFV1CORE_ALTERA implementation. However, there are no architectural changes from the standard V1 ColdFire Core, which means the CFV1CORE_ALTERA fully supports the V1 ColdFire Instruction Set Architecture (ISA_C) and is code-compatible with existing V1 ColdFire devices. The ecosystem for ColdFire including C compiler, BDM debugger, IDE, RTOS and library can be reused on CFV1CORE_ALTERA.

The CFV1CORE_ALTERA IP is fully compatible with Altera’s SOPC Builder and Quartus II tools. That means the designer can quickly and easily build a system from the CFV1CORE_ALTERA and the selected peripheral IP blocks, then generate a bitfile of the whole system and program it onto the Cyclone III device. The software engineer can then download software through the V1 ColdFire single-pin debug interface and start running the application.

• Fully-synthesizable core
• Optimized for the Altera Cyclone III FPGAs, small and robust core, low power, low cost
• SOPC Builder compatible, encrypted RTL source code and SOPC component for the CFV1CORE_ALTERA
• $0 licensing fee and $0 royalty for the core
• Quartus IP license for peripheral blocks
• Commercial support available
• 32-bit processor core with 24-bit address bus with 16MB linear addressing space (upper 8 bits of 32-bit Avalon address bus are 0x00)
• Unified instruction/data bus
• Variable-length RISC architecture with 16-bit, 32-bit, and 48-bit instructions
• Independent, decoupled pipelines
• 2-stage Instruction Fetch Pipeline (IFP)
• 2-stage Operand Execution Pipeline (OEP)
• FIFO Instruction Buffer is the decoupling mechanism
• ColdFire Instruction Set Architecture Rev. C (ISA_C)
• Standard ColdFire user programming model with 16 general-purpose, 32-bit registers
• Simplified supervisor programming model supporting a supervisor stack pointer, vector base register, and CPU configuration register
• Static branch prediction mechanisms minimize change-of-flow execution time
• Execute engines include ALU and barrel shifter (It is my first time to know ColdFire has a barrel shifter!)
• Programmable response upon detection of certain illegal opcodes and illegal addresses (processor exception or system reset)
• ColdFire Debug B+ functionality mapped into the single-pin background debug module (BDM) interface
• Real time debug (RTD) support, with 6 hardware breakpoints (four PC, one address, and one data) that can be configured into a 1- or 2-level trigger with a programmable response (processor halt or interrupt)
• Operating speed, 80MHz (typical)
• Implementation size, 6000 LEs

Optional Features

Because of resource limitation of FPGA, CFV1CORE_ALTERA still remove certain functional blocks from ordinary ColdFire V1. The CFV1CORE_ALTERA is available in a single fixed configuration. 

• The hardware divider (DIV) and multiply-accumulate (MAC) unit are not included in the soft-core. In ColdFire V1 family, MAC, eMAC and DIV functions are also optional, which can reduce the silicon area in regular control oriented space. It is better to have a configurable design to have the optional features.
• The single-pin debug module is included but the 64-entry trace buffer is not, which means program trace is not supported.

Development Kits

Any FPGA based Embedded Development Kit should cover both ecosystems for FPGA and microcontroller devices.

FPGA (Altera)

• SOPC Builder for drag-and-drop IP selection and integration from a rich library
• V1 ColdFire-based hardware reference design as a SOPC Builder project
• A development board with a Cyclone III 2C25 device
• A USB-blaster connector for Altera Quartus II development software (free web edition available) to download the design into FPGA
• Quartus II for synthesis, place-and-route, and device programming
• Cyclone III FPGAs—low-cost 65-nm FPGAs

ColdFire V1 (Freescale)

• Evaluation/development board similar to Altera’s Nios II embedded evaluation kit, but containing a pre-build V1 ColdFire-based hardware reference design (microcontroller, timer, UART and Ethernet MAC) and equipped with a ColdFire debug connector (BDM/JTAG) on a Cyclone III 3C25 device.
• CodeWarrior development tools or IAR Workbench for ColdFire
• A board support package (BSP) for uC/OS-II
• Software reference design (example software)

More and more small companies can have their own SoC since most of the important IP blocks are available now. FPGA was used as the platforms as prototypes and engineering samples for verification and small business. Now more companies use FPGA in final product since the system cost is lower than ASIC approach in highly custom applications. FPGA suppliers define many proprietary microcontrollers, like NIOS, Micro Blaze and more. But using existing ecosystem and code base makes commercial cores an attractive alternatives, including ColdFire V1, ARM7TDMI, Cortex-M1 and 8051 compatible cores. Since many semiconductors have already offered so many microcontrollers, usually you don't bother to design a new one. However, it is a existing challange for an engineer. And in some cases, you will require soft-core for business reason. 

References

Freescale
http://www.freescale.com/webapp/sps/site/overview.jsp?code=CFV1FPGA

Altera
http://www.altera.com/products/ip/processors/32_16bit/m-fre-coldfire-v1....

IPextreme
http://www.ip-extreme.com/IP/coldfire_altera_v1.html

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