Ethernet

The Ethernet is a protocol of CSMA/CD (Carrier Sense Multiple Access/Collision Detect) type developed in 1973, to the purpose of possession the transmissions on the cable reliable in the moderate traffic conditions.

From here derives the standard IEEE 802.3 of the 1985 (the last revision in 2002) that it is from the IEEE 802 protocols big family.
This family defines standard for lots of net typologies (like Token Ring, Token Bus, WiFi, etc.), that's why thought to divide the OSI second level in two levels, the superior, LLc (Logical Link Control), is common at all the standards, while the inferior part , the MAC (Medium Access Control), is tied at the physical level.
The LLC level offers different services usually entrusted to the superior levels and not predicted from the old Ethernet; for this reason, the TCP/IP architecture uses the old framing (named DIX) that doesn't use LLC, while others protocols use the "official" standard.

Addresses MAC and IP
In an Ethernet net, when a packet is send, any system connected to the same net receipts it; it is necessary to identify an ambiguous mode the recipient and the sender (for the answer). This happen thanks to a 6 byte MAC address, associated at the global level to the sole NIC (Network Interfare Controller) or rather each device (network card or another) able to transmitter and receipt the dates in a LAN (Local Area Network).
But, as we know, a computer is identified also from an address IP, but in the locals network a system can be individuate only through its MAC address and so it exists a conversion protocol between these two (ARP protocol).
A NIC, to send a packet to a node of the same network, identifies the recipient MAC address and proceeds; instead the packet is intended to a network outside this one (for example Internet), the gateway MAC address will be used (for example an ADSL router) which provides to forward the dates.
While the IP address can be configured according to the requirements, the MAC address is wrote in NIC in the production phase and usually can't be modified.

The MAC address is divided in two parts of three byte each one: the first one is assigned by IEE to each society which makes the request; the second one is used to generate the different addresses for each card produced from the same society.
Like a didactic purpose we can use the assigned addresses to the Microchip (from 00:04:A3:00:00:00 to 00:04:A3:FF:FF:FF), but for commercials purposes, the addresses are bought.

The MAC level (Datalink)
Let's see how is constituted a MAC plot, or rather the "confectioned" packet from the datalink level in the IEEE 802.3 standard.

• Preamble: Formed of one sequence of 1 and 0 for permit to the receipt to synchronize with the transmitter;
• SFD: Start-of-Frame Delimiter, signalizes to the receipt which starts the true and own plot.
• Destination: Contains the recipient MAC address .
• Source: Contains the sender MAC address.
• Length/Type: According to the standard 802.3 this ares can adopt two different significants: if the value is minor or equal to 1500, suggests the dates area length where it supposed to be present a LLC packet which will be precessed by the under par homonym, otherwise indicates the third level protocol contained in the dates area; in this last case the MAC plot is a DIX plot, so doesn't follow the LLC transport, but the dates are passed straight at the third level.
• Data: here are contained the date passed from the superior level; the minimum length is of 46 byte, if this limit isn't respected, in the transmission phase the MAC level adds a padding area to load the remaining space.
• FCS Frame Check Sequence, constituted from 4 byte for the errors control (CRC).

The ENC28J60 controller
The ENC28J60 Microchip is a Ethernet 10Base-T (10Mbps duplicated) controller, sticking to the IEEE 802.3 standard.
It is constituted from a PHY (physical level) module, a MAC (MAC under level) module, a 8byte RAM memory to take in the packets in reception and in transmission and a module for the serial SPI communication
The chip has just 28pin and needs a few externals components, that's why can be simply inserted in any project.

Revisions and Errata
The ENC28J60, like each chip from Microchip, has a revision number (REVID), so each chip with a certain REVID can have some differences compared to a chip with another number.
To know the chip version there two ways: the first is to read an internal register between SPI interface; the second is to ask the Microchip assistance , which can find the REVID between the serial at seven-figure under the chip.
The revision more recent is at B5, and until now is possible to create software and hardware in such way not to concern the review number; the only thing that changes at hardware level is a resistance which we'll see it a little bit later.
Beyond the controller datasheet a very important document is theErrata (relative at each review): here there are presented some chip problemes and relatives solutions, as well as the differences between a review and another.
The hardware
This is the circuit scheme realized by me to write this article.

The ENC28J60 is fueled by a 3.3V (max 180mA) tension, so there are some various possible configurations:

• To fuel all the circuit (PIC included) at 3.3V, can be used a PIC18F25J10 or similar, which can work at 40Mhz also at this tension; others PIC, instead, function just at minors frequency.
• Fueling the PIC at 5V, there are necessary some level adapters (simple logical ports CMOS, 74HC08 type), for the ENC exits which go to PIC (SO, CLKOUT, INT, WOL); the controller (CS, SCK, SI, RESET) entrances are tolerant at 5V.
• The PIC, usually, have like threshold value a logical value 1 at entrance of 2V, that's why these level translators would not seem indispensable, like is described in ENC28J60 datasheet , so in my scheme aren't presented.

The controller is projected to work at 25Mhz, that's why is necessary a quartz of this frequency between the OSC1 and OSC2 pins, plus two ceramic condensers connected to the ground. The value of these condensers ins't specified in the datasheet, but I presume is around 15pF.
Can be also used an external clock, connected at OSC1 pic, but it must be very precise (+/- 50ppm).

An important component is RBIAS, its value changes after the chip review: for the B1-B4 review is of 2.7Kohm 1%, while for the B5 is of 2.32K 1%; its value it's important to respect the IEE specifics, that's why is good to be sure that you have it (we'll see how).
The datasheet names a "ferrite bead", but doesn't specify the value: in my scheme I replaced it with an inductance from 1mH.

The last important components are the RJ45 connector and the relatives filters (Magnetics): there are connectors with the filters integrated, or connector and filters apart.
In my case I used a connector ERNI with the filters integrated (attention to the scheme, the pin could be various from another connector type).
In each case is indispensable to follow with attention the scheme presented in the datasheet, which I return it followed (the transformers 1:1 are the Filters):

The Magnetics are some little black cases which can recover (with the connector) from the network card.

About hardware:
- The INT (interrupt) pin isn't used by the software, that's why if you don't intend to exploit the interruption can be not connect.
- The ENC28J60 has between its characteristics theauto-polarity, or rather the pin TPIN+ and TPIN-, even reversed, function the same; in fact it isn't true (the problem is described in the Errata), so is advisable an accurate control of these pins in circuit planning/montage phase
- The datasheet advises to insert ceramic condensers from 0.1uF, for every couple of Vcc-Vss pins.

Organization of the Memory
The chip memory is divided in two parts: the rx/tx buffer and the control registers. To the both it is approached through the SPI interface.
The buffer is a dual port RAM, configurable to be able to divide it to your taste, between the reception memory and the transmission one.
The control registers structure resumes that one already present in the PIC: this is constituted from a registers series at 8bit, divided in frames, through is possible to configure the device.
These are divided in registers ETH, MAC, MII and PHY; the first three are found in the benches of registries, while registries PHY it is approached through registries MII.

We will see the function of several registries as we will make use of it.
Read also:
Ethernet 1/7