PCI Express is a very popular interface standard with the transfer rate ranging from 500MBit/s to 8GBit/s (PCIe 2.0) in each direction, providing a high-speed bus for many devices such as graphics cards, sound cards, NICs, and Modems for computers and other embedded applications. By taking advantage of the standard’s high-speed switch mechanism, PCI Express has almost replaced the general-purpose PCI expansion bus, the high-end PCI-X bus and the AGP graphics card interface.

The original PCI standard is a busbased system in which all the devices share the same bidirectional, 32-bit (or 64-bit), parallel signal path. It is like a narrow road with one direction opened at a time and the traffi c has to wait until the bus system is free. The PCI Express system architecture is a layered protocol and compatible with the PCI standard, consisting of a physical layer, data link layer, transaction layer and software layer. It is designed to natively support “Hot-Plug” function through the “Hot-Plug sense” signal. A PCI Express link is built on pairs of serial, uni-directional point-topoint connections known as “lanes”.

A PCI Express 2.0 (currently the most common version) slot is like a greatly widened bidirectional highway with many lanes. Each lane has its dedicated bandwidth and can send information at a rate of 500MBit/s in each direction. Each PCI Express slot carries either one, two, four, eight, sixteen or thirty-two lanes of data between the motherboard and the add-in card, which means the highest bandwidth could be up to 16GBit/s in each direction. Putting this in perspective, a single lane for PCI Express 2.0 has nearly four times the bandwidth of PCI 2.1 (133MBit/s, a four-lane slot has nearly twice the bandwidth of the PCI-X fastest version at1066MBit/s), and an eight-lane slot has nearly twice the bandwidth of the AGP fastest version (2133MBit/s).

Common Buses and their Max Bandwidth

Note: The number in the bracket is the combined bandwidth in both directions.

Why does it work so fast?
A connection between any two PCI Express devices is known as a “link”, and is built up from a collection of 1 or more lanes. Each lane includes 2 differential pairs; one is for Transmit Express is a serial bus which enables it to work easily at an extremely high speed without any interference. Under the full duplex mode, the PCI Express bus can support a data rate of up to 16GBit/s for PCI Express x32. It also benefits from the 8b/10b decoding scheme and the clocking information is embedded in the signal, which efficiently saves the transfer lanes and improves the data transfer efficiency. Finally, the performance is also derived from Peer-to-Peer mode. Every PCI Express device has dedicated bandwidth; there is no need to apply for the bandwidth on the bus, which eliminates several devices simultaneously contending for the use of the whole bandwidth.

PCIe Suppliers
PCI Express has replaced PCI and AGP as the most common interface on new PC and Server systems since it was fi rst published on January 15, 2007. The standard is supported by CPU and Chipset manufactures such as Intel, AMD, VIA and SiS in many product lines. Pericom and IDT provide supporting equipment for PCIe devices like Switches, Bridges, Clocks, Repeaters and Re-drivers. Some Programmable PCI Express solutions based on FPGA and PCIe Phy have been developed by ST-NXP Wireless, Xilinx, Lattice and Genesys Logic, Altera and TI. From its original roots in the PC and server markets, the PCI Express standard has been introduced into other areas such as consumer electronics by ST-NXP and Broadcom.

Source: Technology First
By Michael Luo, Premier Farnell Global Technical Centre, China