DSP (digital signal processing) on FPGA - Let's see the advantages and disadvantages!

First let’s see the maximum speed that can be achieved by the processing scheme. Well, the answer is given by a simple rule: the maximum speed of a chain is imposed by the slowest link, which is the ADC. The commercial ADCs sampling rate is limited to 250MSample/sec (for example Linear Technology). Of course you can find ADC having 10GSamples/sec throughput, but can you afford it? The Nyquist sampling theorem says the sampling frequency should be at least 2 times higher than the highest frequency component in the sampled signal, but in practice oversampling is recommended. So the analog signal that can be filtered has the maximum frequency component around 25 MHz. This is way enough for home appliance or educational applications. Usually the digital to analog conversion is not a concern; the DACs can work at higher rates than the ADCs.

FPGAs are highly flexible circuits that can work at high frequencies, but the most important thing is the possibility of parallel processing. Sounds promising, but to accomplish digital filtering is a long process, requiring digital filter design knowledge and working experience with FPGA.

Unlike DSPs, the FPGA doesn’t have incorporated ADC nor DACs. The designer’s task is to connect the conversion devices to the FPGA by implementing some buffer zone most likely in HDL (VHDL or Verilog). The most of the stand alone ADCs have an industry standard protocol as an integrated interface, like SPI or I2C. Some engineers will get lucky and they will use IP cores that are already written and tested. But for sure some will have to write their own interfaces. This task seems to be a routine work; theoretically the interface is a big state machine, what everybody can make in few days. Problems will appear when you have to make the interface compatible with DMA controllers or you have to connect to an industry standard bus, you never heard about. Do not be scared! Digital filter, as FIR or IIR, implementation doesn’t need sophisticated interfacing with converters.

Now let’s focus on some digital filter design issues. Digital filters are working at a defined sampling frequency. My recommendation is to choose the ADC’s and the filter’s sampling frequency equal. In this case only continuous data flow and data integrity must be assured. One can see that the ADC interface must provide the samples at a constant rate. The samples than are processed by the digital filter. To compute the coefficients of the digital filter many filter design applications can be used. Another big difference between the DSPs and FPGAs arise, because usually the filter’s coefficients are real, not integer, values. The DSPs can work with floating point representation, easing the computation of the filter response. Also on FPGAs the use of floating point cores is possible, but it will take up huge area inside the FPGA when real parallel processing is desired (additional control circuit can be built around the floating point operation unit to pipeline the operations, but this will increase the necessary cycles to compute the response). To get rid of the floating point operations you can scale the coefficients values to and round them to integer ones. This will result in the decrease of occupied aria and wont increase the computation cycles.

The main advantage that FPGA can present is the processing speed. If the digital filter fits in the FPGA and no additional tricks are required to use the same core for multiple operations, than filter response is computed in 1 cycle (the cycle time of the sampling rate)!

Finally a short overview: A trivial processing chain for digital filtering was presents. The ADC’s sampling rate defines the digital filters working frequency. After the calculus of the digital filter’s coefficients they must be scaled in order to work with integer values inside the FPGA. This may be difficult, but area is saved. It seems there is too much work with digital filter implementation in FPGAs, but you can achieve filter response in 1 cycle…

In the upcoming post I will present digital filter design using MATLAB. See you soon!

## But will the FPGA be able to

But will the FPGA be able to compensate the laxity of the ADC to stabiize the flow of the DAC? (In reference to mhz frequencies)

## Yes, you can compensate for that.

In most Digital Signal Processing applications the slowest link in the chain is the ADC. The DAC can keep up with the conversion of the output signal. Depending on the application other kind of distortions can appear. If the designer knows the behavior of the distortions than compensation filters or algorithms can be implemented on FPGAs.

Botond Sandor Kirei