Description

The TMS320DM6467 (also referenced as DM6467) is a Digital Media System-on-Chip. It leverages TI's DaVinci technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6467 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.
The dual-core architecture of the DM6467 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates:
• A coprocessor 15 (CP15) and protection module
• Data and program Memory Management Units (MMUs) with table look-aside buffers.
• Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 5832 million instructions per second (MIPS) at a clock rate of 729 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.

The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide(literature number SPRU732).

The DM6467 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6467 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.
The DM6467 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

Features

• High-Performance Digital Media SoC
• 594-, 729-MHz C64x+™ Clock Rate
• 297-, 364.5-MHz ARM926EJ-Strade; Clock Rate
• Eight 32-Bit C64x+ Instructions/Cycle
• 4752, 5832 C64x+ MIPS
• Fully Software-Compatible With C64x/ARM9™
• Supports SmartReflex™ Class 0 [-594 only]
o 1.05-V and 1.2-V Adaptive Core Voltage
• Extended Temp Available [-594 only]
• Industrial Temp Available [-729 only]
• Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
• Eight Highly Independent Functional Units
o Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
o Two Multipliers Support Four 16 ×: 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
• Load-Store Architecture With Non-Aligned Support
• 64 32-Bit General-Purpose Registers
• Instruction Packing Reduces Code Size
• All Instructions Conditional
• Additional C64x+™ Enhancements
o Protected Mode Operation
o Exceptions Support for Error Detection and Program Redirection
o Hardware Support for Modulo Loop Operation
• ARM9 Memory Architecture
• 16K-Byte Instruction Cache
• 8K-Byte Data Cache
• 32K-Byte RAM
• 8K-Byte ROM
• Embedded Trace Buffer™ (ETB11™) With 4KB Memory for ARM9 Debug
• Endianness: Little Endian for ARM and DSP
• Dual Programmable High-Definition Video Image Co-Processor (HDVICP) Engines
• Supports a Range of Encode, Decode, and Transcode Operations
o H.264, MPEG2, VC1, MPEG4 SP/ASP
• External Memory Interfaces (EMIFs)
• 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
• Asynchronous16-Bit Wide EMIF (EMIFA) With 128M-Byte Address Reach
o Flash Memory Interfaces
- NOR (8-/16-Bit-Wide Data)
- NAND (8-/16-Bit-Wide Data)
• Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
• Programmable Default Burst Size
• USB Port With Integrated 2.0 PHY
• USB 2.0 High-/Full-Speed Client
• USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)
• 32-Bit, 33-MHz, 3.3 V Peripheral Component Interconnect (PCI) Master/Slave Interface
• Conforms to PCI Specification 2.3
• Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
• One 64-Bit Watch Dog Timer
• One Serial Peripheral Interface (SPI) With Two Chip-Selects
• Master/Slave Inter-Integrated Circuit (I2C Bus™)
• Two Multichannel Audio Serial Ports (McASPs)
• One Four Serializer Transmit/Receive Port
• One Single DIT Transmit Port for S/PDIF
• 32-Bit Host Port Interface (HPI)
• VLYNQ™ Interface (FPGA Interface)
• Two Pulse Width Modulator (PWM) Outputs
• ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
• Up to 33 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
• On-Chip ARM ROM Bootloader (RBL)
• Individual Power-Saving Modes for ARM/DSP
• Flexible PLL Clock Generators
• IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
• 529-Pin Pb-Free BGA Package (ZUT Suffix), 0.8-mm Ball Pitch
• 0.09-µm/7-Level Cu Metal Process (CMOS)
• 3.3-V and 1.8-V I/O, 1.2/1.05-V Internal

Applications:

• Video Encode/Decode/Transcode/Transrate
• Digital Media
• Networked Media Encode/Decode
• Video Imaging
• Video Infrastructure
• Video Conferencing

TMS320DM6467