In a previous article we have seen the basic concepts related to the CRC (Cyclic Redundancy Check) calculation and its importance in providing a protection against accidental data corruption. Scope of this article is to show how those concepts have been applied on a commercial microcontroller family: the Flexis AC by Freescale.

This family of MCU is the newest entry in the Freescale Controller Continuum, which ensures pin-pin hardware and software compatibility among several models of processors, from 8- up to 32-bits.

Cyclic Redundancy Check can be easily calculated through a software procedure and the previous article described the simplest version of this algorithm, based on the usage of a left-shift register and an iteration of bitwise XOR operations. That algorithm can be quickly implemented in a high-level language (such as C, for example) requiring only few lines of code. The performance, however, are not very good: it requires a lot of iterations and it could slow-down a not so fast microcontroller. Just to give you an idea, consider that the software algorithm requires at least 700 bus cycles to process just a single byte of the data message. That’s why, remaining at the software level, another algorithm, based on a pre-formatted lookup table, has been introduced: it is faster and can be practically ported on any microcontroller. However, we have focused on the “simple” version of the CRC computation processing, because, when implemented at the hardware level, it becomes very efficient and fast.

Data protection is a very important issue in today’s embedded systems: lots of data is exchanged at high data rate among processors and peripherals, or is stored on a flash file systems; in order to avoid any usage of bad or corrupted data, a validation control such as the CRC has become necessary.

The CRC module provided with the Freescale AC family is compliant to the CRC16-CCITT specifications, which is based on the following polynomial generator: x¹⁶+x¹²+x⁵+1. That means it is able to detect all single, double, odd, and most multi-bit errors. Performance measurements done by Freescale show that, on a MC9S08AC128 Flexis AC MCU running at 20 MHz, the CRC calculation of 128 Kb of flash performed via software requires about 6.7 seconds, whereas the some processing performed via hardware requires only 170 ms: that’s a significant improvement.
As already stated in the previous article regarding the CRC basic concepts, we recall that the computation of a cyclic redundancy check is derived from the mathematics of:

• Polynomial division
• Modulo 2 arithmetic – addition and subtraction are executed without carries and borrows, that means they can be done with exclusive OR operand

That means that the CRC is obtained dividing the stream of data bytes by the polynomial generator, considering both of them as an ordered sequence of bits.

Flexis AC CRC implementation

The CRC computation algorithm is not so complicated: it basically consists of exclusive OR and shift operations. The modulo two arithmetic helps a lot the calculation: a division is performed through shift operations, whereas subtraction is performed through an exclusive OR operation. A hardware implementation, therefore, will require a shift register with a number of bits equal to the polynomial degree, plus a XOR gate on each bit corresponding to a ‘1’ in the polynomial generator coefficients. The Flexis AC CRC module is compliant to the CRC16-CCITT specifications; that means that the polynomial generator (with width W equal to 16) is x16+x12+x5+1, corresponding to the hexadecimal value 0x1021 (conventionally, the highest bit set to 1 is omitted in the representation). The following figure shows how the hardware implementation of the CRC module has been designed in the Flexis AC MCU:

As shown in the block diagram, the CRC module uses only two registers, CRCH and CRCL. When the CRC calculation is started, a programmable seed value is loaded into register CRCH:L; the CRC16-CCITT standard, for instance, uses a seed value equal to 0xFFFF. Once the seed has been loaded, the algorithm can proceed in the following way. Each byte of the message is loaded into register CRCL; that triggers the CRC module which loads each byte (starting from the MSB) into the shift register, the procedure shall be repeated until all bytes have been processed. At this point, the CRCH:L register contains the calculated CRC. A new computation can be started writing a new seed value to CRCH:L. It should be noticed that other seed values can be chosen; the value 0xFFFF is compliant to the CRC16-CCITT standard, but other common values such as 0x102D and 0x0000 can be adopted.

Read the Italian version: Il modulo CRC della famiglia Freescale Flexis AC

Reference

Freescale AN3795 – Using the CRC Module on the Flexis AC Family
This Application Note provides a detailed explanation of the Flexis AC CRC module, including a full example code written in C.

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