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Very Low-Jitter Encoded Clocking for High Speed ADCs Using the ADF4002 PLL

By Ionela Apr 16th, 2009
Very Low-Jitter Encoded Clocking for High Speed ADCs Using the ADF4002 PLL

This article discusses a design example using the ADF4002 frequency synthesizer to generate a very low-jitter clock to control sampling on Analog Devices’ AD9215 ADC.
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