Here are some more I/O specific techniques for static consumption. Try reducing the switch capacitances and frequencies of I/Os, decouple I/Os when you're in the sleep mode.

This article provides an overview of the sources of FPGA power dissipation, design practices that can help reduce consumption and thus junction temperature, how to estimate and analyze power, and then some tips for managing a variety of power sources required for an FPGA implementation.

Programmable logic has now become a critical component for the design community, moving from the prototyping stage into general designs.

Xilinx announced that it will provide a live demonstration of its next-generation 100GE interface with best-in-class ecosystem support for core, metro, data center and access aggregation network applications.

Unlike physical hardware, the equivalent logic circuitry embedded in an FPGA can’t be probed, tested and monitored in the conventional way.

The ultimate goal is to create a FPGA logic analyzer for the home. The system would include actual analyzer for a Spartan 3 FPGA and PC software for the user.

Lattice Semiconductor launched the 40 Gbps SERDES Framer Interface, Level 5 (SFI5) Intellectual Property (IP) Core in the LatticeSC and LatticeSCM FPGA families.