The DS28E01-100 combines 1024 bits of EEPROM organized as four 256-bit pages, a 64-bit secret, a register page, a 512-bit SHA-1 engine, and a 64-bit ROM registration number in a single chip. Data is transferred serially through the 1-Wire protocol, which requires only a single data lead and a ground return. The DS28E01-100 has an additional memory area called the scratchpad that acts as a buffer when writing to the memory, the register page, or when installing a new secret. Data is first written to the scratchpad from where it can be read back. After the data has been verified, a copy scratchpad command transfers the data to its final memory location, provided that the DS28E01-100 receives a matching 160-bit MAC.

The computation of the MAC involves the secret and additional data stored in the DS28E01-100 including the device’s registration number. Only a new secret can be loaded without providing a MAC. The SHA-1 engine is also activated to compute 160-bit MACs when performing an authenticated read of a memory page and when computing a new secret, instead of loading it.

The DS28E01-100 understands a unique command “Refresh Scratchpad.” Proper use of a refresh sequence after a copy scratchpad operation reduces the number of weak bit failures if the device is used in a touch environment (see the Writing with Verification section). The refresh sequence also provides a means to restore functionality in a device with bits in a weak state.

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